公开(公告)号：US11874569B2

公开(公告)日：2024-01-16

申请号：US17743101

申请日：2022-05-12

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Han Ho Park ,  Dae Geun Lee ,  Su Jeong Kim ,  Sang Won Yeo ,  Kyung Mok Lee ,  Wu Hyen Jung

IPC: G02F1/1345 ,  G09F9/35 ,  H01L23/00 ,  H05K1/11 ,  H05K3/32 ,  G02F1/1333

CPC classification number: G02F1/13452 ,  G02F1/13458 ,  G09F9/35 ,  H01L24/06 ,  H05K1/117 ,  H05K1/118 ,  H05K3/321 ,  G02F1/13454 ,  G02F1/133305 ,  H01L2224/50 ,  H01L2224/79 ,  H01L2224/86 ,  H01L2225/06579 ,  H05K2201/09427 ,  H05K2201/10128 ,  H05K2201/10681

Abstract: A display device includes a substrate, conductive pads arranged on the substrate over a plurality of rows, and a drive circuit chip including bumps arranged over a plurality of rows to be electrically connected with the conductive pads, and the conductive pads arranged in a same row are arranged in parallel, and the bumps arranged in a same row are arranged in a zigzag form so as to be partially shifted.

公开(公告)号：US20180359864A1

公开(公告)日：2018-12-13

申请号：US16003474

申请日：2018-06-08

Applicant: PITYU CONTROLS INC.

Inventor： Stevan DOBI

IPC: H05K3/34 ,  H05K1/18 ,  B23K1/00

CPC classification number: H05K3/3442 ,  B23K1/0016 ,  B23K2101/42 ,  H05K1/181 ,  H05K2201/09381 ,  H05K2201/09427 ,  H05K2201/10022 ,  H05K2201/10174 ,  H05K2201/10583 ,  H05K2203/048

Abstract: A cradle for a metal electrode leadless face (MELF) device is provided. The cradle can include at least one pad, such as a solder pad, to be connected to a printed circuit board (PCB) or similar board. The pad can be configured to receive a MELF device. Such a configuration can improve positioning and alignment of the MELF device and prevent or reduce movement of the MELF device prior to or during soldering. The pad can include boundaries to engage the MELF device for alignment and to prevent or reduce movement. The boundaries of the pad can include inlets, extensions, troughs, borders, and/or other features to engage the MELF device. Boards including such cradles are also provided. Further, methods of installing a MELF device on a board using a cradle are also provided.

公开(公告)号：US09576728B2

公开(公告)日：2017-02-21

申请号：US13918512

申请日：2013-06-14

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Young Ghyu Ahn ,  Sang Soo Park ,  Min Cheol Park ,  Se Hwa Jeong

IPC: H05K1/16 ,  H01G4/005 ,  H05K1/02 ,  H01G4/30

CPC classification number: H01G4/005 ,  H01G4/30 ,  H05K1/0271 ,  H05K1/111 ,  H05K3/3442 ,  H05K2201/09427 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2201/2045 ,  Y02P70/611

Abstract: A laminated chip electronic component includes: a ceramic body including internal electrodes and dielectric layers; external electrodes formed to cover both end portions of the ceramic body in a length direction; an active layer in which the internal electrodes are disposed in an opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; and upper and lower cover layers formed on upper and lower portions of the active layer in a thickness direction, the lower cover layer having a thickness greater than that of the upper cover layer.

Abstract translation: 层叠芯片电子部件包括：陶瓷体，其包括内部电极和电介质层; 形成为在长度方向上覆盖陶瓷体的两端部的外部电极; 其中内部电极以相对的方式设置在其间插入电介质层的有源层以形成电容; 以及在有源层的厚度方向的上部和下部形成的上部和下部覆盖层，所述下部覆盖层的厚度大于上部覆盖层的厚度。

公开(公告)号：US09516751B2

公开(公告)日：2016-12-06

申请号：US14417751

申请日：2013-05-17

Applicant: NGK SPARK PLUG CO., LTD.

Inventor： Takahiro Hayashi ,  Makoto Nagai ,  Seiji Mori ,  Tomohiro Nishida ,  Makoto Wakazono ,  Tatsuya Ito

IPC: H05K1/11 ,  G03F7/20 ,  G03F7/30 ,  H05K1/02 ,  G03F7/038 ,  H01L23/498 ,  H05K3/34 ,  H05K3/46

CPC classification number: H05K1/111 ,  G03F7/038 ,  G03F7/20 ,  G03F7/2024 ,  G03F7/30 ,  H01L23/49822 ,  H01L2224/16237 ,  H05K1/0298 ,  H05K3/3436 ,  H05K3/3452 ,  H05K3/4644 ,  H05K2201/09409 ,  H05K2201/09427 ,  H05K2201/09709 ,  H05K2201/09845 ,  H05K2201/099 ,  H05K2201/10674 ,  H05K2203/058 ,  H05K2203/0594 ,  H05K2203/1476

Abstract: To provide a wiring board excellent in connection reliability with a semiconductor chip. A first buildup layer 31 where resin insulating layers 21 and 22 and a conductor layer 24 are laminated is formed at a substrate main surface 11 side of an organic wiring board 10. The conductor layer 24 for an outermost layer in the first buildup layer 31 includes a plurality of connecting terminal portions 41 for flip-chip mounting a semiconductor chip. The plurality of connecting terminal portions 41 is exposed through an opening portion 43 of a solder resist layer 25. Each connecting terminal portion 41 includes a connection region 51 for a semiconductor chip and a wiring region 52 disposed to extend from the connection region 51 along the planar direction. The solder resist layer 25 includes, within the opening portion 43, a side-surface covering portion 55 that covers the side surface of the connecting terminal portion 41 and a projecting wall portion 56 that is integrally formed with the side-surface covering portion 55 and disposed to project so as to intersect with the connection region 51.

Abstract translation: 提供与半导体芯片的连接可靠性优异的布线板。 在有机布线板10的基板主表面11侧形成有树脂绝缘层21,22和导体层24层叠的第一堆积层31.第一堆积层31中的最外层的导体层24包括 多个用于倒装芯片安装半导体芯片的连接端子部分41。 多个连接端子部分41通过阻焊层25的开口部分43露出。每个连接端子部分41包括用于半导体芯片的连接区域51和从连接区域51延伸的布线区域52 平面方向。 阻焊层25在开口部43内具有覆盖连接端子部41的侧面的侧面覆盖部55和与侧面覆盖部55一体形成的突出壁部56， 被设置为突出以与连接区域51相交。

公开(公告)号：US09451710B2

公开(公告)日：2016-09-20

申请号：US13047592

申请日：2011-03-14

Applicant: Sanghun Park

Inventor： Sanghun Park

IPC: H05K3/36 ,  H01M2/26 ,  H01M2/22 ,  H01M10/42 ,  H01M2/10 ,  H05K3/34 ,  H01M2/20

CPC classification number: H05K3/363 ,  H01M2/202 ,  H01M2/22 ,  H01M2/26 ,  H01M10/425 ,  H05K3/3426 ,  H05K2201/09427 ,  H05K2201/10037

Abstract: A battery pack includes a connection circuit board connected to the unit cells, a conductive lead drawn out from the connection circuit board, a printed circuit module having an opening into which the conductive lead is inserted, a solder portion formed by solder connection in which the conductive lead is inserted into the opening, wherein the conductive lead has an insertion portion inserted into the opening, a bent portion bent from the insertion portion, and a recess by which the insertion portion is divided.

Abstract translation: 电池组包括连接到单电池的连接电路板，从连接电路板引出的导电引线，具有导电引线插入的开口的印刷电路模块，通过焊料连接形成的焊料部分，其中 导电引线插入到开口中，其中导电引线具有插入开口的插入部分，从插入部分弯曲的弯曲部分和插入部分被分开的凹部。

公开(公告)号：US20160233189A1

公开(公告)日：2016-08-11

申请号：US15023716

申请日：2013-09-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshikazu SHIMOTE ,  Shinji BABA ,  Toshihiro IWASAKI ,  Kazuyuki NAKAGAWA

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L24/17 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/562 ,  H01L23/564 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05572 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16055 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/1713 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2224/83 ,  H01L2224/83104 ,  H01L2224/85 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/05442 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/186 ,  H01L2924/2064 ,  H01L2924/351 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/068 ,  H05K2201/09427 ,  H05K2201/10704 ,  H05K2201/10977 ,  H05K2203/0465 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2224/45099 ,  H01L2924/207

Abstract: In a semiconductor device (SP1) according to an embodiment, a solder resist film (first insulating layer, SR1) which is in contact with the base material layer, and a resin body (second insulating layer, 4) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (2CR) of a wiring substrate 2 and a semiconductor chip (3). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body. Also, the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the resin body. According to the above-described configuration, damage of the semiconductor device caused by a temperature cyclic load can be suppressed, and thereby reliability can be improved.

Abstract translation: 在根据实施例的半导体器件（SP1）中，与基材层接触的阻焊膜（第一绝缘层SR1）和与该基材层接触的树脂体（第二绝缘层4） 阻焊膜和半导体芯片层叠在布线基板2的基材层（2CR）和半导体芯片（3）之间。 此外，阻焊膜的线膨胀系数等于或大于基材层的线膨胀系数，阻焊膜的线膨胀系数等于或小于 树脂体。 此外，基材层的线膨胀系数小于树脂体的线膨胀系数。 根据上述结构，可以抑制由温度循环负载引起的半导体器件的损坏，从而可以提高可靠性。

公开(公告)号：US20160163456A1

公开(公告)日：2016-06-09

申请号：US15042272

申请日：2016-02-12

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Kyo Kwang LEE ,  Sang Soo PARK ,  Young Ghyu AHN ,  Byoung Hwa LEE

IPC: H01G4/012 ,  H05K1/18 ,  H05K1/11 ,  H01G4/12 ,  H01G4/30

CPC classification number: H01G4/005 ,  H01G2/065 ,  H01G4/012 ,  H01G4/12 ,  H01G4/232 ,  H01G4/30 ,  H05K1/111 ,  H05K1/181 ,  H05K2201/09427 ,  H05K2201/10015 ,  Y02P70/611

Abstract: A multilayer ceramic capacitor may include: a ceramic body including dielectric layers and having first and second main surfaces opposing each other, first and second side surfaces opposing each other, and first and second end surfaces opposing each other; an active layer configured to form capacitance by including first and second internal electrodes disposed to face each other with the dielectric layer interposed therebetween and alternately exposed to the first or second side surface; and a first external electrode disposed on the first side surface and electrically connected to the first internal electrodes and a second external electrode disposed on the second side surface and electrically connected to the second internal electrodes. When length of the ceramic body is L and length of the first and second external electrodes in the length direction of the ceramic body is L1, 0.2≦L1/L≦0.96 is satisfied.

Abstract translation: 多层陶瓷电容器可以包括：陶瓷体，其包括电介质层，并且具有彼此相对的第一和第二主表面，彼此相对的第一和第二侧表面以及彼此相对的第一和第二端面; 有源层，被配置为通过包括彼此相对设置的第一和第二内部电极来形成电容，所述第一和第二内部电极介于其间并交替地暴露于第一或第二侧表面; 以及第一外部电极，设置在第一侧面上并与第一内部电极电连接，第二外部电极设置在第二侧面上并电连接到第二内部电极。 当陶瓷体的长度为L，陶瓷体的长度方向上的第一外部电极和第二外部电极的长度为L1时，满足0.2≤nlE; L1 / L＆lt; nlE; 0.96。

公开(公告)号：US20160148911A1

公开(公告)日：2016-05-26

申请号：US14903858

申请日：2014-07-08

Applicant: PSI CO., LTD.

Inventor： Young Rag Do

IPC: H01L25/075 ,  H01L33/38 ,  H01L33/62

CPC classification number: H01L25/0753 ,  H01L33/38 ,  H01L33/62 ,  H01L2924/0002 ,  H01L2933/0066 ,  H05K1/0295 ,  H05K1/0296 ,  H05K1/111 ,  H05K3/3442 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09381 ,  H05K2201/0939 ,  H05K2201/09427 ,  H05K2201/09954 ,  H05K2201/10106 ,  H05K2201/10583 ,  H05K2201/10636 ,  H05K2201/10651 ,  H05K2203/048 ,  Y02P70/611 ,  H01L2924/00

Abstract: Provided are a nano-scale LED assembly and a method for manufacturing the same. First, a nano-scale LED device that is independently manufactured may be aligned and connected to two electrodes different from each other to solve a limitation in which a nano-scale LED device having a nano unit is coupled to two electrodes different from each other in a stand-up state. Also, since the LED device and the electrodes are disposed on the same plane, light extraction efficiency of the LED device may be improved. Furthermore, the number of nano-scale LED devices may be adjusted. Second, since the nano-scale LED device does not stand up to be three-dimensionally coupled to upper and lower electrodes, but lies to be coupled to two electrodes different from each other on the same plane, the light extraction efficiency may be very improved. Also, since a separate layer is formed on a surface of the LED device to prevent the LED device and the electrode from being electrically short-circuited, defects of the LED electrode assembly may be minimized. Also, in preparation for the occurrence of the very rare defects of the LED device, the plurality of LED devices may be connected to the electrode to maintain the original function of the nano-scale LED electrode assembly.

Abstract translation: 提供了一种纳米级LED组件及其制造方法。 首先，独立制造的纳米级LED器件可以对准并连接到彼此不同的两个电极，以解决将具有纳米单元的纳米级LED器件耦合到彼此不同的两个电极的限制 站立状态。 此外，由于LED器件和电极设置在同一平面上，所以可以提高LED器件的光提取效率。 此外，可以调整纳米级LED器件的数量。 第二，由于纳米尺度的LED器件不能立即连接到上电极和下电极，而是要被连接到在同一平面上彼此不同的两个电极，所以光提取效率可以非常改善 。 此外，由于在LED器件的表面上形成单独的层以防止LED器件和电极电短路，所以可以使LED电极组件的缺陷最小化。 此外，为了准备LED装置的非常罕见的缺陷的发生，可以将多个LED器件连接到电极以保持纳米级LED电极组件的原始功能。

公开(公告)号：US20150366049A1

公开(公告)日：2015-12-17

申请号：US14526182

申请日：2014-10-28

Applicant: Samsung Display Co., Ltd.

Inventor： Dae Geun LEE

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11

CPC classification number: H01L27/124 ,  G02F1/13458 ,  H01L24/05 ,  H01L24/06 ,  H01L24/81 ,  H01L27/3276 ,  H01L2224/05552 ,  H01L2224/06152 ,  H01L2224/81132 ,  H01L2924/3511 ,  H05K1/111 ,  H05K1/189 ,  H05K2201/09381 ,  H05K2201/09418 ,  H05K2201/09427 ,  H05K2201/09709 ,  H05K2201/09954 ,  H05K2201/10128 ,  H05K2203/166 ,  Y02P70/611 ,  Y10T29/49005

Abstract: An array substrate including a display area and a non-display area surrounding the display area. The non-display area includes a pad portion including one or more first pads that each have a parallelogram shape.

Abstract translation: 阵列基板，包括显示区域和围绕显示区域的非显示区域。 非显示区域包括包括一个或多个每个具有平行四边形形状的第一焊盘的焊盘部分。

公开(公告)号：US20150342045A1

公开(公告)日：2015-11-26

申请号：US14718094

申请日：2015-05-21

Applicant: NICHIA CORPORATION

Inventor： Takuya NAKABAYASHI ,  Akira HORI

IPC: H05K1/11 ,  H05K1/18 ,  F21V8/00

CPC classification number: H05K1/111 ,  G02B6/0066 ,  G02B6/0073 ,  H05K1/181 ,  H05K3/3442 ,  H05K2201/09381 ,  H05K2201/09427 ,  H05K2201/09472 ,  H05K2201/09745 ,  H05K2201/10106 ,  H05K2201/10454 ,  H05K2203/048 ,  Y02P70/611

Abstract: A semiconductor device mounting structure includes a semiconductor device and a mounting substrate. The semiconductor device includes a first external connection terminal and a device-side mounting insulating region. The first external connection terminal is provided at a first end and has a metal region on a semiconductor mounting surface of the semiconductor device. The device-side mounting insulating region is defined by the metal region on the semiconductor mounting surface. The semiconductor mounting surface faces a substrate mounting surface. The mounting substrate has on the substrate mounting surface a land pattern made of an electrically conductive material to be electrically connected to the first external connection terminal. The land pattern is provided in a first shape to surround the device-side mounting insulating region and includes a land-side insulating region which has a second shape to correspond to a periphery of the device-side mounting insulating region.

Abstract translation: 半导体器件安装结构包括半导体器件和安装基板。 半导体器件包括第一外部连接端子和器件侧安装绝缘区域。 第一外部连接端子设置在第一端，并且在半导体器件的半导体安装表面上具有金属区域。 器件侧安装绝缘区域由半导体安装表面上的金属区域限定。 半导体安装表面面向基板安装表面。 安装基板在基板安装表面上具有由导电材料制成的焊盘图案，以电连接到第一外部连接端子。 所述焊盘图案设置成围绕所述器件侧安装绝缘区域的第一形状，并且包括具有与所述器件侧安装绝缘区域的周边相对应的第二形状的焊盘侧绝缘区域。