公开(公告)号：US10529554B2

公开(公告)日：2020-01-07

申请号：US15592730

申请日：2017-05-11

Applicant: ASM IP Holding B.V.

Inventor： Dai Ishikawa ,  Atsuki Fukazawa ,  Eiichiro Shiba ,  Shinya Ueda ,  Taishi Ebisudani ,  SeungJu Chun ,  YongMin Yoo ,  YoonKi Min ,  SeYong Kim ,  JongWan Choi

IPC: H01L21/02 ,  H01L21/306 ,  H01L21/311

Abstract: A method for fabricating a layer structure in a trench includes: simultaneously forming a dielectric film containing a Si—N bond on an upper surface, and a bottom surface and sidewalls of the trench, wherein a top/bottom portion of the film formed on the upper surface and the bottom surface and a sidewall portion of the film formed on the sidewalls are given different chemical resistance properties by bombardment of a plasma excited by applying voltage between two electrodes between which the substrate is place in parallel to the two electrodes; and substantially removing either one of but not both of the top/bottom portion and the sidewall portion of the film by wet etching which removes the one of the top/bottom portion and the sidewall portion of the film more predominantly than the other according to the different chemical resistance properties.

公开(公告)号：US20190249303A1

公开(公告)日：2019-08-15

申请号：US16252567

申请日：2019-01-18

Applicant: ASM IP Holding B.V.

Inventor： Aurélie Kuroda ,  Atsuki Fukazawa

IPC: C23C16/455 ,  C23C16/40

CPC classification number: C23C16/45553 ,  C07F7/0838 ,  C07F7/10 ,  C23C16/402 ,  C23C16/45538

Abstract: A chemical precursor and a method for depositing a silicon oxide film on a surface of a substrate within a reaction space by plasma-enhanced atomic layer deposition are disclosed. The chemical precursors may include a Si—O—Si skeleton or a Si—N—Si skeleton.

公开(公告)号：US09818601B1

公开(公告)日：2017-11-14

申请号：US15278797

申请日：2016-09-28

Applicant: ASM IP Holding B.V.

Inventor： Masaki Tokunaga ,  Masaru Zaitsu ,  Atsuki Fukazawa

IPC: H01L21/31 ,  H01L21/02 ,  C23C16/455 ,  C23C16/50 ,  C23C16/52

CPC classification number: H01L21/02274 ,  C23C16/45536 ,  C23C16/45544 ,  C23C16/45548 ,  C23C16/45565 ,  C23C16/50 ,  C23C16/52 ,  H01J37/32357 ,  H01J37/3244 ,  H01J37/32449 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228

Abstract: A substrate processing apparatus includes a chamber, a stage provided in the chamber, a shower head in which a plurality of slits are formed, and which is opposed to the stage, an opening/closing part for opening and closing the plurality of slits, a first gas supply part which supplies a gas to a space between the stage and the shower head via the plurality of slits, and a second gas supply part which is connected to a side wall of the chamber, and which supplies a gas to the space between the stage and the shower head.

公开(公告)号：US09754779B1

公开(公告)日：2017-09-05

申请号：US15048422

申请日：2016-02-19

Applicant: ASM IP Holding B.V.

Inventor： Dai Ishikawa ,  Atsuki Fukazawa

IPC: H01L21/44 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/0217 ,  C23C16/045 ,  C23C16/345 ,  C23C16/45536 ,  C23C16/505 ,  C23C16/56 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3105 ,  H01L21/31111

Abstract: A method for fabricating a layer structure in a trench includes: simultaneously forming a dielectric film containing a Si—N bond on an upper surface, and a bottom surface and sidewalls of the trench, wherein a top/bottom portion of the film formed on the upper surface and the bottom surface and a sidewall portion of the film formed on the sidewalls are given different chemical resistance properties by bombardment of a plasma excited by applying voltage between two electrodes between which the substrate is place in parallel to the two electrodes; and substantially removing either one of but not both of the top/bottom portion and the sidewall portion of the film by wet etching which removes the one of the top/bottom portion and the sidewall portion of the film more predominantly than the other according to the different chemical resistance properties.

公开(公告)号：US20170051405A1

公开(公告)日：2017-02-23

申请号：US14829565

申请日：2015-08-18

Applicant: ASM IP Holding B.V.

Inventor： Atsuki Fukazawa ,  Hideaki Fukuda

IPC: C23C16/455 ,  C23C16/44 ,  C23C16/505 ,  C23C16/34

CPC classification number: C23C16/45536 ,  C23C16/045 ,  C23C16/345 ,  C23C16/36 ,  C23C16/45553 ,  C23C16/5096

Abstract: A method for forming a SiN or SiCN film in a trench on a substrate by plasma-enhanced atomic layer deposition (PEALD) conducts one or more process cycles, each process cycle including: (i) feeding a precursor in a pulse to a reaction space where the substrate is place, said precursor having a Si—N—Si bond in its skeletal structure to which at least one halogen group is attached; and (ii) applying RF power to the reaction space in the presence of a reactant gas and in the absence of any precursor to form a monolayer constituting a SiN or SiCN film.

Abstract translation: 通过等离子体增强的原子层沉积（PEALD）在衬底上的沟槽中形成SiN或SiCN膜的方法进行一个或多个工艺循环，每个工艺循环包括：（i）将脉冲中的前体供给到反应空间 所述前体在其骨架结构中具有至少一个卤素基团的Si-N-Si键; 和（ii）在反应气体的存在下和在不存在任何前体的情况下将RF功率施加到反应空间以形成构成SiN或SiCN膜的单层。

公开(公告)号：US09455138B1

公开(公告)日：2016-09-27

申请号：US14937053

申请日：2015-11-10

Applicant: ASM IP Holding B.V.

Inventor： Atsuki Fukazawa ,  Hideaki Fukuda ,  Noboru Takamure ,  Masaru Zaitsu

IPC: H01L21/311 ,  H01L21/02

CPC classification number: H01L21/0228 ,  H01L21/02123 ,  H01L21/02211 ,  H01L21/02274

Abstract: A method for forming a dielectric film in a trench on a substrate by plasma-enhanced atomic layer deposition (PEALD) performs one or more process cycles, each process cycle including: (i) feeding a silicon-containing precursor in a pulse; (ii) supplying a hydrogen-containing reactant gas at a flow rate of more than about 30 sccm but less than about 800 sccm in the absence of nitrogen-containing gas; (iii) supplying a noble gas to the reaction space; and (iv) applying RF power in the presence of the reactant gas and the noble gas and in the absence of any precursor in the reaction space, to form a monolayer constituting a dielectric film on a substrate at a growth rate of less than one atomic layer thickness per cycle.

Abstract translation: 通过等离子体增强原子层沉积（PEALD）在衬底上的沟槽中形成电介质膜的方法执行一个或多个工艺循环，每个工艺循环包括：（i）以脉冲方式供给含硅前体; （ii）在不存在含氮气体的情况下以大于约30sccm但小于约800sccm的流量供应含氢反应气体; （iii）向反应空间供应惰性气体; 和（iv）在反应气体和惰性气体的存在下，在反应空间中不存在任何前体的情况下施加RF功率，以在小于一个原子的生长速率下在衬底上形成构成电介质膜的单层 每个周期的层厚度。

公开(公告)号：US11646197B2

公开(公告)日：2023-05-09

申请号：US16986274

申请日：2020-08-06

Applicant: ASM IP Holding B.V.

Inventor： Timothee Julien Vincent Blanquart ,  Mitsuya Utsuno ,  Yoshio Susa ,  Atsuki Fukazawa ,  Toshio Nakanishi

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/762 ,  C23C16/26 ,  C23C16/455 ,  C23C16/50

CPC classification number: H01L21/0228 ,  C23C16/26 ,  C23C16/45542 ,  C23C16/50 ,  H01L21/02115 ,  H01L21/02205 ,  H01L21/02274 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76837

Abstract: A film having filling capability is deposited by forming a viscous polymer in a gas phase by striking an Ar, He, or N2 plasma in a chamber filled with a volatile hydrocarbon precursor that can be polymerized within certain parameter ranges which define mainly partial pressure of precursor during a plasma strike, and wafer temperature.

公开(公告)号：US11626316B2

公开(公告)日：2023-04-11

申请号：US16950899

申请日：2020-11-17

Applicant: ASM IP Holding B.V.

Inventor： Mitsuya Utsuno ,  Yan Zhang ,  Yoshio Susa ,  Atsuki Fukazawa

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/311 ,  C23C16/26 ,  C23C16/455 ,  C23C16/50 ,  C23C16/04 ,  C23C16/56

Abstract: Methods and systems for filling a recess on a surface of a substrate with carbon-containing material are disclosed. Exemplary methods include forming a first carbon layer within the recess, etching a portion of the first carbon layer within the recess, and forming a second carbon layer within the recess. Structures formed using the method or system are also disclosed.

公开(公告)号：US11127589B2

公开(公告)日：2021-09-21

申请号：US16752514

申请日：2020-01-24

Applicant: ASM IP Holding B.V.

Inventor： Masaru Zaitsu ,  Atsuki Fukazawa

IPC: H01L21/02 ,  H01L21/311

Abstract: A method for forming a dielectric film containing a Si—O bond a trench formed in an upper surface of a substrate, includes: designing a topology of a final dielectric film containing a Si—O bond formed in the trench by preselecting a target portion to be selectively removed relative to a non-target portion of an initial dielectric film resulting in the final dielectric film; conformally depositing the initial dielectric film on the upper surface and in the trench; and relatively increasing an amount of impurities contained in the target portion of the initial dielectric film relative to an amount of impurities contained in the non-target portion of the initial dielectric film to obtain a treated dielectric film, thereby giving the target portion and the non-target portion different chemical resistance properties when subjected to etching.

公开(公告)号：US11056345B2

公开(公告)日：2021-07-06

申请号：US15847681

申请日：2017-12-19

Applicant: ASM IP Holding B.V.

Inventor： Atsuki Fukazawa

IPC: H01L21/285 ,  C23C16/455 ,  C23C16/34 ,  C23C16/517 ,  C23C16/06

Abstract: Examples of a method for manufacturing a semiconductor device include forming an initial film having a film thickness of 1 to 3 nm made of a metal or a metal nitride by applying plasma film formation with plasma power of 0.07 to 0.30 W/cm2 and an RF pulse width within a range of 0.1 to 1 sec, and forming, after forming the initial film, a bulk film made of a metal or metal nitride on the initial film by applying plasma film formation with plasma power higher than the plasma power when the initial film is formed.