公开(公告)号：US20230112432A1

公开(公告)日：2023-04-13

申请号：US17564747

申请日：2021-12-29

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： John J. Wuu ,  Jaroslaw Kuszczak ,  Gaurav Singla

IPC: G06F3/06

Abstract: A system and method for efficiently capturing data by sequential circuits across multiple operating conditions are described. In various implementations, an integrated circuit includes multiple signal arrival adjusters both at its I/O boundaries and across its die. The signal arrival adjuster includes two internal timing paths, each with a respective latency. The signal arrival adjuster receives an input signal, and generates an output signal from the a selected one of the first timing path and the second timing path. The signal arrival adjuster sends the output signal to a sequential circuit. The sequential circuit uses the output signal as one of an input data signal and an input clock signal. The selection between the two timing paths within the signal arrival adjuster aids satisfying the setup and hold time requirements of the sequential circuit.

公开(公告)号：US11527270B2

公开(公告)日：2022-12-13

申请号：US17359253

申请日：2021-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： John J. Wuu ,  Russell J. Schreiber

IPC: G11C7/00 ,  G11C7/10 ,  H03K19/173 ,  G11C7/12

Abstract: A static random access memory (SRAM) includes fast SRAM bit cells and fast multiplexer circuits that are formed in a first row of fast cells in a hybrid standard cell architecture. Slow SRAM bit cells and slow multiplexer circuits are formed in a second row of slow cells. The slow multiplexer circuits provide a column output for the fast SRAM bit cells and the fast multiplexer circuits provide a column output for the slow SRAM bit cells. Thus, one SRAM column has fast bit cells and slow multiplexer stages while the adjacent SRAM column has slow bit cells and fast multiplexer stages to thereby provide an improved performance balance when reading the SRAM.

公开(公告)号：US20220358996A1

公开(公告)日：2022-11-10

申请号：US17359254

申请日：2021-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell J. Schreiber ,  John J. Wuu

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4074 ,  G11C7/10

Abstract: A write masked latch bit cell of an SRAM includes a write mask circuit that is responsive to assertion of a first write mask signal to cause a value of a write data node to be a first value and is responsive to assertion of a second write mask signal to cause the value of the write data node to have a second value. A pass gate supplies the data on the write data node to an internal node of the bit cell responsive to write word line signals being asserted. A keeper circuit maintains the value of the first node independently of values of the write word line signals while the first write mask signal and the second write mask signal are deasserted.

公开(公告)号：US20220093504A1

公开(公告)日：2022-03-24

申请号：US17030830

申请日：2020-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz ,  John J. Wuu

IPC: H01L23/528 ,  H01L27/11 ,  H01L23/522 ,  G11C11/418 ,  G11C11/419 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A layout for a 6T SRAM cell is disclosed. The cell layout takes a conventional 6T SRAM cell layout and restructures the layout into a more square cell layout with a single p-channel and a single n-channel across the width of the cell. Restructuring the cell layout reduces the height of wordlines and allows dual wordlines to be placed in the cell to reduce wordline resistance in the cell. Dual pairs of bitlines may also be placed in separate metal layers in the cell layout to reduce bitline resistance.

公开(公告)号：US10366734B2

公开(公告)日：2019-07-30

申请号：US15424418

申请日：2017-02-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander W. Schaefer ,  Ravi T. Jotwani ,  Samiul Haque Khan ,  David Hugh McIntyre ,  Stephen Victor Kosonocky ,  John J. Wuu ,  Russell Schreiber

IPC: G11C8/08 ,  G11C11/418 ,  G11C5/14 ,  G11C11/413 ,  G11C11/419

Abstract: A system and method for efficient power, performance and stability tradeoffs of memory accesses under a variety of conditions are described. A system management unit in a computing system interfaces with a memory and a processing unit, and uses boosting of word line voltage levels in the memory to assist write operations. The computing system supports selecting one of multiple word line boost values, each with an associated cross-over region. A cross-over region is a range of operating voltages for the memory used for determining whether to enable or disable boosting of word line voltage levels in the memory. The system management unit selects between enabling and disabling the boosting of word line voltage levels based on a target operational voltage for the memory and the cross-over region prior to updating the operating parameters of the memory to include the target operational voltage.

公开(公告)号：US10311191B2

公开(公告)日：2019-06-04

申请号：US15416731

申请日：2017-01-26

Applicant: Advanced Micro Devices, Inc.

Inventor： John J. Wuu ,  Patrick J. Shyvers ,  Ryan Alan Selby

IPC: G06F17/50 ,  G11C7/06 ,  G11C7/20 ,  G11C5/02

Abstract: A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory. The size of each memory line in the memory includes M bits. A memory macro block includes at least a primary array and a sidecar array. The primary array stores a first portion of a memory line and the sidecar array stores a second smaller portion of the memory line being accessed. The primary array and the sidecar array have different heights. The height of the sidecar array is based on a notch height in at least one corner of the memory macro block. The notch creates on-die space for s reserved area on the die. The notches result in cross-shaped, T-shaped, and/or L-shaped memory macro blocks.

公开(公告)号：US09953687B1

公开(公告)日：2018-04-24

申请号：US15299709

申请日：2016-10-21

Applicant: Advanced Micro Devices, Inc.

Inventor： John J. Wuu ,  Ryan Freese ,  Russell J. Schreiber

IPC: G11C11/41 ,  G11C11/419 ,  G11C7/12 ,  H03K19/0185 ,  G11C7/06 ,  G11C7/22

CPC classification number: G11C7/12 ,  G11C5/14 ,  G11C7/08 ,  G11C7/222 ,  G11C7/225 ,  H03K19/00323 ,  H03K19/018507

Abstract: An interlock circuit utilizes a single combinatorial pseudo-dynamic logic gate to take inputs from two voltage domains at the same time without requiring either input to be level shifted. The interlock design allows hold timing to be met across a large voltage range of both supplies in a dual-voltage supply environment while not significantly hurting setup time by having much lower latency than the latency of a level shifter.