公开(公告)号：US10790241B2

公开(公告)日：2020-09-29

申请号：US16289072

申请日：2019-02-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang ,  Yan Wen Chung ,  Huei-Shyong Cho

IPC: H05K1/11 ,  H05K3/42 ,  H01L23/00 ,  H01L23/498 ,  H01L23/552 ,  H01L21/48 ,  H01L21/66 ,  H01L21/683 ,  H01L23/66 ,  H01L25/16

Abstract: A wiring structure includes a conductive structure, a surface structure and at least one through via. The conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The surface structure is disposed adjacent to a top surface of the conductive structure. The through via extends through the surface structure and extending into at least a portion of the conductive structure.

公开(公告)号：US10522492B2

公开(公告)日：2019-12-31

申请号：US15614563

申请日：2017-06-05

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang ,  Yan Wen Chung ,  Chien-Mei Huang

IPC: H01L23/00 ,  H01L23/522 ,  H01L21/768 ,  H01L23/14 ,  H01L23/04 ,  H01L23/498 ,  H01L21/3213

Abstract: A wiring structure includes a dielectric layer and a first patterned conductive layer on the dielectric layer. The dielectric layer has a first region and a second region. The first patterned conductive layer includes a number of fine conductive lines and a number of dummy conductive structures. The number of conductive lines include a first number of conductive lines on the first region and a second number of conductive lines on the second region, and the number of dummy conductive structures include a first number of dummy conductive structures on the second region. The first number of conductive lines occupy a first area on the first region, and the second number of conductive lines and the first number of dummy conductive structures occupy a second area on the second region. A ratio of the second area to the first area is greater than or equal to about 80%.

公开(公告)号：US09984986B1

公开(公告)日：2018-05-29

申请号：US15432814

申请日：2017-02-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang

IPC: H01L25/03 ,  H01L23/00

CPC classification number: H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0225 ,  H01L2224/02255 ,  H01L2224/03011 ,  H01L2224/03614 ,  H01L2224/0401 ,  H01L2224/06188 ,  H01L2224/13026

Abstract: A semiconductor device includes a substrate, a patterned conductive layer on the substrate, a passivation layer on the substrate and surrounding the patterned conductive layer, a first under bump metallurgy (UBM) and a second UBM on the passivation layer and electrically connected to the patterned conductive layer, and an isolation structure on the passivation layer and between the first UBM and the second UBM.

公开(公告)号：US12300677B2

公开(公告)日：2025-05-13

申请号：US18231767

申请日：2023-08-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Mei Huang ,  Shih-Yu Wang ,  I-Ting Lin ,  Wen Hung Huang ,  Yuh-Shan Su ,  Chih-Cheng Lee ,  Hsing Kuo Tien

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.

公开(公告)号：US12021044B2

公开(公告)日：2024-06-25

申请号：US17067556

申请日：2020-10-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang

IPC: H01L23/66 ,  H01L21/48 ,  H01L23/498 ,  H01Q1/22

CPC classification number: H01L23/66 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49838 ,  H01Q1/2283 ,  H01L2223/6677

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first conductive component, a second conductive component, a planarization layer and an antenna layer. The second conductive component is disposed adjacent to the first conductive component. The second conductive component and the first conductive component have different thicknesses. The planarization layer is disposed on the first conductive component. The antenna layer is disposed on the first conductive component and the second conductive component.

公开(公告)号：US11908815B2

公开(公告)日：2024-02-20

申请号：US17724422

申请日：2022-04-19

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01Q1/22 ,  H01L23/00

CPC classification number: H01L23/66 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/562 ,  H01Q1/2283 ,  H01L2223/6677

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes an antenna layer, a first circuit layer and a second circuit layer. The antenna layer has a first coefficient of thermal expansion (CTE). The first circuit layer is disposed over the antenna layer. The first circuit layer has a second CTE. The second circuit layer is disposed over the antenna layer. The second circuit layer has a third CTE. A difference between the first CTE and the second CTE is less than a difference between the first CTE and the third CTE.

公开(公告)号：US11894293B2

公开(公告)日：2024-02-06

申请号：US17384290

申请日：2021-07-23

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49833 ,  H01L21/4857 ,  H01L23/49822

Abstract: A circuit structure and an electronic structure are provided. The circuit structure includes a low-density conductive structure, a high-density conductive structure and an electrical connection structure. The high-density conductive structure is disposed on the low-density conductive structure. The electrical connection structure extends through the high-density conductive structure and is electrically connected to the low-density conductive structure. The electrical connection structure includes a shoulder portion.

公开(公告)号：US11430750B2

公开(公告)日：2022-08-30

申请号：US16425702

申请日：2019-05-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang ,  Min Lung Huang ,  Yuh-Shan Su

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01Q1/22

Abstract: A semiconductor device package includes a first substrate, an antenna, a support layer, a dielectric layer and a second substrate. The first substrate has a first surface and a second surface opposite to the first surface. The antenna element is disposed on the second surface of the first substrate. The support layer is disposed on the first surface of the first substrate and at the periphery of the first surface of the first substrate. The support layer has a first surface facing away from the first substrate. The dielectric layer is disposed on the first surface of the support layer and spaced apart from the first substrate. The dielectric layer is chemically bonded to the support layer. The second substrate is disposed on a first surface of the dielectric layer facing away from the support layer.

公开(公告)号：US11322471B2

公开(公告)日：2022-05-03

申请号：US16681500

申请日：2019-11-12

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang

IPC: H01L23/00

Abstract: A semiconductor package structure includes a first substrate, a second substrate, a first redistribution layer, and a first reconnection layer. The first substrate may have a first surface. The second substrate can be spaced apart from the first substrate with a gap and may have a second surface. The first redistribution layer can be disposed between the first redistribution layer and the gap. The first substrate can be electrically connected to the second substrate via the first reconnection layer.

公开(公告)号：US11211325B2

公开(公告)日：2021-12-28

申请号：US16696825

申请日：2019-11-26

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang ,  Yan Wen Chung ,  Min Lung Huang

IPC: H01L23/522 ,  H01L23/498 ,  H01L23/31 ,  H01L21/768 ,  H01L21/56 ,  H01L21/027 ,  H01L23/00 ,  H01L21/48

Abstract: A semiconductor package may include a first substrate and a second substrate, a redistribution layer (RDL), a first conductive via and a second conductive via. The first substrate has a first surface and a second surface opposite to the first surface. The second substrate has a first surface and a second surface opposite to the first surface. The RDL is disposed on the first surface of the first substrate and the first surface of the second substrate. The first conductive via passes through the RDL and is electrically connected to the first substrate. The second conductive via passes through the RDL and is electrically connected to the second substrate.