公开(公告)号：US06429119B1

公开(公告)日：2002-08-06

申请号：US09405059

申请日：1999-09-27

Applicant: Li-Chih Chao ,  Chia-Shiung Tsai ,  Ming-Huei Lui ,  Jen-Cheng Liu ,  Chao-Cheng Chen

Inventor： Li-Chih Chao ,  Chia-Shiung Tsai ,  Ming-Huei Lui ,  Jen-Cheng Liu ,  Chao-Cheng Chen

IPC: H01L214763

CPC classification number: H01L21/76808 ,  H01L21/76813 ,  H01L2221/1063

Abstract: Using this special dual damascene process, interconnect conducting lines and via contacts are formed which have low parasitic capacitance (low RC time constants). The invention incorporates the use of thin etch stop or etch barrier layers. The key process steps of this invention are a special partial via hole etch and a special via hole liner. The Prior Art dual damascene processes are generally composed of a thick via etch stop layer to avoid damaging underlying Cu during via patterning, as well as, a thick trench etch stop layer to avoid via hole facet during trench patterning. Thick etch stop layers are undesirably due to high dielectric constant values compared with silicon oxide, the intermetal dielectric (IMD). Therefore, the thickness of stop-layer should be reduced to minimize the circuit (RC) time constant delay. In general, there are two main approaches for dual damascene etching. One of the main approaches use self-aligned dual damascene (SADD) etching which requires a thick trench etching stop-layer thickness. The other approach use counter-bore method which requires a thick via etching stop-layer thickness. This invention describes a novel dual damascene process which can minimize the thickness of both via and trench etching stop-layer, while avoiding deleterious damage to the underlying to and via facet profile during via and trench etching.

Abstract translation: 使用这种特殊的双镶嵌工艺，形成具有低寄生电容（低RC时间常数）的互连导线和通孔触点。 本发明包括使用薄蚀刻停止层或蚀刻阻挡层。 本发明的关键工艺步骤是特殊的部分通孔蚀刻和特殊通孔衬垫。 现有技术的双镶嵌工艺通常由厚的通孔蚀刻停止层组成，以避免在通孔图案化期间损坏下面的铜，以及在沟槽图案化期间避免通孔小面的厚沟槽蚀刻停止层。 与氧化硅（金属间电介质（IMD））相比，由于高的介电常数值，厚的蚀刻停止层是不期望的。 因此，应该减小停止层的厚度以最小化电路（RC）时间常数延迟。 一般来说，双镶嵌蚀刻有两种主要方法。 主要方法之一使用自对准双镶嵌（SADD）蚀刻，其需要厚沟槽蚀刻停止层厚度。 另一种方法使用需要厚通孔蚀刻停止层厚度的反孔法。 本发明描述了一种新颖的双镶嵌工艺，其可以最小化通孔和沟槽蚀刻停止层的厚度，同时避免在通孔和沟槽蚀刻期间对于底面和经过小面轮廓的有害损伤。

公开(公告)号：US06319822B1

公开(公告)日：2001-11-20

申请号：US09164999

申请日：1998-10-01

Applicant: Chao-Cheng Chen ,  Chia-Shiung Tsai ,  Shau-Lin Shue ,  Hun-Jan Tao

Inventor： Chao-Cheng Chen ,  Chia-Shiung Tsai ,  Shau-Lin Shue ,  Hun-Jan Tao

IPC: H01L214763

CPC classification number: H01L21/76831 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/76802

Abstract: A method for etching of sub-quarter micron openings in insulative layers for contacts and vias is described. The method uses hardmask formed of carbon enriched titanium nitride. The hardmask has a high selectivity for etching contact and via openings in relatively thick insulative layers. The high selectivity requires a relatively thin hardmask which can be readily patterned by thin photoresist masks, making the process highly desirable for DUV photolithography. The hardmask is formed by MOCVD using a metallorganic titanium precursor. By proper selection of the MOCVD deposition conditions, a controlled amount of carbon is incorporated into the TiN film. The carbon is released as the hardmask erodes during plasma etching and participates in the formation of a protective polymer coating along the sidewalls of the opening being etched in the insulative layer. The protective sidewall polymer inhibits lateral chemical etching and results in openings with smooth, straight, and near-vertical sidewalls without loss of dimensional integrity.

Abstract translation: 描述了用于在接触和通孔的绝缘层中蚀刻二分之一微米开口的方法。 该方法使用由富碳氮化钛形成的硬掩模。 硬掩模在相对较厚的绝缘层中对蚀刻接触和通孔的选择性很高。 高选择性需要相对薄的硬掩模，其可以通过薄的光致抗蚀剂掩模容易地图案化，使得该工艺对于DUV光刻非常期望。 硬掩模由MOCVD使用金属有机钛前体形成。 通过适当选择MOCVD沉积条件，将受控量的碳纳入TiN膜中。 在等离子体蚀刻期间，随着硬掩模腐蚀而释放碳，并且参与沿着在绝缘层中蚀刻的开口的侧壁形成保护性聚合物涂层。 保护性侧壁聚合物抑制侧向化学蚀刻并导致具有平滑，直的和近垂直的侧壁的开口，而不损失尺寸完整性。

公开(公告)号：US6025273A

公开(公告)日：2000-02-15

申请号：US55433

申请日：1998-04-06

Applicant: Chao-Cheng Chen ,  Chia-Shiung Tsai ,  Hun-Jan Tao

Inventor： Chao-Cheng Chen ,  Chia-Shiung Tsai ,  Hun-Jan Tao

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L21/283

CPC classification number: H01L21/31144 ,  H01L21/76816 ,  H01L23/5226 ,  H01L21/0332 ,  H01L21/31116 ,  H01L2924/0002

Abstract: A method is achieved for fabricating small contact holes in an interlevel dielectric (ILD) layer for integrated circuits. The method increases the ILD etch rate while reducing residue build-up on the contact hole sidewall. This provides a very desirable process for making contact holes small than 0.25 um in width. After depositing the ILD layer over the partially completed integrated circuit which includes patterned doped first polysilicon layers, a second polysilicon layer is deposited and doped with carbon by ion implantation. A photoresist mask is used to etch openings in the carbon doped polysilicon layer to form a hard mask. The photoresist is removed, and the contact holes are plasma etched in the ILD layer while free carbon released from the hard mask, during etching, reduces the free oxygen in the plasma. This results in an enhanced fluorine (F.sup.+) etch rate for the contact holes in the ILD layer and reduces the residue build-up on the sidewalls of the contact holes. The hard mask is anneal in O.sub.2 to form an oxide layer and any surface carbon is removed in a wet etch. Reliable metal plugs can now be formed by depositing a barrier layer, such as titanium (Ti) or titanium nitride (TiN) and a metal such as tungsten (W) and etching back or chemical/mechanical polishing back to the oxide layer.

Abstract translation: 实现了用于在用于集成电路的层间电介质（ILD）层中制造小接触孔的方法。 该方法增加了ILD蚀刻速率，同时减少了接触孔侧壁上的残留物积聚。 这提供了使接触孔宽度小于0.25μm的非常理想的方法。 在包括图案化掺杂的第一多晶硅层的部分完成的集成电路上沉积ILD层之后，通过离子注入沉积第二多晶硅层并掺杂碳。 光致抗蚀剂掩模用于蚀刻碳掺杂多晶硅层中的开口以形成硬掩模。 去除光致抗蚀剂，并且在ILD层中对接触孔进行等离子体蚀刻，而在蚀刻期间从硬掩模释放出的游离碳降低了等离子体中的游离氧。 这导致ILD层中的接触孔的氟（F +）蚀刻速率增加，并减少了接触孔的侧壁上的残留物积聚。 硬掩模在O 2中退火以形成氧化物层，并且在湿蚀刻中除去任何表面碳。 现在可以通过沉积诸如钛（Ti）或氮化钛（TiN）和诸如钨（W）的金属的阻挡层并且将氧化物层回蚀刻或化学/机械抛光来形成可靠的金属插塞。

公开(公告)号：US6008131A

公开(公告)日：1999-12-28

申请号：US995340

申请日：1997-12-22

Applicant: Chao-Cheng Chen

Inventor： Chao-Cheng Chen

IPC: H01L21/3065 ,  H01L21/762 ,  H01L21/302

CPC classification number: H01L21/3065 ,  H01L21/76232

Abstract: A method of forming shallow isolation trenches in integrated circuit wafers which prevents wafer damage due to dislocations or the like occurring at sharp corners at the intersection between the sidewalls and bottom of the trench. A trench is formed in the wafer using a series of reactive ion etching steps. The bottom of the trench is then etched using reactive ion etching with etching parameters chosen to produce dry isotropic etching. The dry isotropic etching of the bottom of the trench results in a rounded bottom and sharp corners between the sidewalls and bottom of the trench are avoided.

Abstract translation: 在集成电路晶片中形成浅隔离沟槽的方法，其防止由于在沟槽的侧壁和底部之间的交叉处的尖角处发生位错等的晶片损坏。 使用一系列反应离子蚀刻步骤在晶片中形成沟槽。 然后使用反应离子蚀刻蚀刻沟槽的底部，并且选择蚀刻参数以产生干各向同性蚀刻。 沟槽底部的干各向同性腐蚀导致圆形的底部，并避免了沟槽的侧壁和底部之间的尖角。

公开(公告)号：US5994229A

公开(公告)日：1999-11-30

申请号：US5567

申请日：1998-01-12

Applicant: Chao-Cheng Chen ,  Chia-Shiung Tsai

Inventor： Chao-Cheng Chen ,  Chia-Shiung Tsai

IPC: H01L21/3065 ,  H01L21/762

CPC classification number: H01L21/3065 ,  H01L21/76232

Abstract: A process for forming a shallow trench having steep sidewalls near its bottom and sloping sidewalls at the top is described. The process is in 3 stages. The first stage involves methane trifluoride, carbon tetrafluoride, argon, and oxygen. The second stage involves methane trifluoride and methane monofluoride, while the third stage involves hydrogen bromide, chlorine, and helium/oxygen. If the ratio of the various components at each stage is carefully controlled along with other variables such as discharge power, pressure, and duration, the trench profile described above is obtained with a minimum of deposited polymer material on the sidewalls.

Abstract translation: 描述了一种用于形成在其底部附近具有陡峭侧壁并且在顶部具有倾斜侧壁的浅沟槽的工艺。 这个过程分3个阶段。 第一阶段涉及三氟化甲烷，四氟化碳，氩气和氧气。 第二阶段涉及甲烷三氟化氢和甲烷单氟化物，而第三阶段涉及溴化氢，氯气和氦气/氧气。 如果每个阶段的各种组分的比例与诸如放电功率，压力和持续时间的其他变量一起被仔细地控制，则上述的沟槽轮廓是通过在侧壁上沉积的最少的聚合物材料获得的。

公开(公告)号：US5981398A

公开(公告)日：1999-11-09

申请号：US58122

申请日：1998-04-10

Applicant: Chia-Shiung Tsai ,  Chao-Cheng Chen ,  Hun-Jan Tao

Inventor： Chia-Shiung Tsai ,  Chao-Cheng Chen ,  Hun-Jan Tao

IPC: H01L21/3213 ,  H01L21/3065

CPC classification number: H01L21/32136 ,  H01L21/32137 ,  H01L21/32139

Abstract: A method for forming a chlorine containing plasma etched patterned layer. There is first provided a substrate 10 employed within a microelectronics fabrication. There is then formed over the substrate a blanket target layer 12 formed of a material susceptible to etching within a second plasma employing a chlorine containing etchant gas composition. There is then formed upon the blanket target a blanket hard mask layer 14 formed of a material selected from the group consisting of silsesquioxane spin-on-glass (SOG) materials and amorphous carbon materials. There is then formed upon the blanket hard mask layer a patterned photoresist layer 16. There is then etched while employing the patterned photoresist layer as a first etch mask layer and while employing a first plasma employing a fluorine containing etchant gas composition the blanket hard mask layer to form a patterned hard mask layer. Finally, there is then etched while employing at least the patterned hard mask layer as a second etch mask layer and while employing the second plasma employing the chlorine containing etchant gas composition the blanket target layer to form the patterned target layer.

Abstract translation: 一种形成含氯等离子体蚀刻图案层的方法。 首先提供了在微电子制造中使用的衬底10。 然后在衬底上形成由使用含氯蚀刻剂气体组合物在第二等离子体内易于蚀刻的材料形成的覆盖层目标层12。 然后在橡皮布目标上形成由选自倍半硅氧烷旋涂玻璃（SOG）材料和无定形碳材料的材料形成的橡皮布硬掩模层14。 然后在橡皮布硬掩模层上形成图案化的光致抗蚀剂层16.然后在使用图案化的光致抗蚀剂层作为第一蚀刻掩模层的同时进行蚀刻，并且在使用含氟蚀刻剂气体组合物的第一等离子体的同时， 以形成图案化的硬掩模层。 最后，在使用至少图案化的硬掩模层作为第二蚀刻掩模层的同时蚀刻，并且在使用含氯蚀刻剂气体组合物的第二等离子体时，覆盖目标层以形成图案化目标层。

公开(公告)号：US20230015410A1

公开(公告)日：2023-01-19

申请号：US17455033

申请日：2021-11-16

Applicant: Chao-Cheng Chen

Inventor： Chao-Cheng Chen

IPC: A61K31/716 ,  A61K9/70 ,  A61K35/74 ,  A61P1/04

Abstract: Provided is a method of preventing or treating gastroesophageal reflux disease, including administering to an subject in need thereof a composition including a plurality of fibers formed of β-1-4-glucan, wherein the fibers have a diameter between 15 nm and 35 nm and a mean length of between 1.5 μm and 3.5 μm.

公开(公告)号：US20220284685A1

公开(公告)日：2022-09-08

申请号：US17674004

申请日：2022-02-17

Applicant: Chao-Cheng Chen ,  Chao-Yu Chen

Inventor： Chao-Cheng Chen ,  Chao-Yu Chen

IPC: G06T19/20 ,  G06T7/00 ,  G06T7/10

Abstract: In many applications, the assessment of the internal structures of tubular structures (such as in medical imaging, blood vessels, bronchi, and colon) has become a topic of high interest. Many 3D visualization techniques, such as “fly-through” and curved planar reformation (CPR), have been used for visualization of the lumens for medical applications. However, all the existing visualization techniques generate highly distorted images of real objects. This invention provides direct manipulation based on the centerline of the object and visualization of the 3D internal structures of a tubular object without any noticeable distortion. For the first time ever, the lumens of a human colon is visualized as it is in reality. In many medical applications, this can be used for diagnosis, planning of surgery or stent placements, etc. and consequently improves the quality of healthcare significantly. The same technique can be used in many other applications.

公开(公告)号：US09287179B2

公开(公告)日：2016-03-15

申请号：US13353975

申请日：2012-01-19

Applicant: Yuan-Sheng Huang ,  Tzu-Yen Hsieh ,  Ming-Ching Chang ,  Chao-Cheng Chen ,  Chia-Jen Chen

Inventor： Yuan-Sheng Huang ,  Tzu-Yen Hsieh ,  Ming-Ching Chang ,  Chao-Cheng Chen ,  Chia-Jen Chen

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L29/66545 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure involves a FinFET. The FinFET includes a fin structure formed over a substrate. A gate dielectric layer is least partially wrapped around a segment of the fin structure. The gate dielectric layer contains a high-k gate dielectric material. The FinFET includes a polysilicon layer conformally formed on the gate dielectric layer. The FinFET includes a metal gate electrode layer formed over the polysilicon layer. The present disclosure provides a method of fabricating a FinFET. The method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure. The method includes forming a polysilicon layer over the gate dielectric layer, wherein the polysilicon layer is formed in a conformal manner. The method includes forming a dummy gate layer over the polysilicon layer.

Abstract translation: 本公开涉及FinFET。 FinFET包括在衬底上形成的翅片结构。 栅介质层最少部分地缠绕在翅片结构的一段上。 栅介质层包含高k栅介质材料。 FinFET包括在栅介质层上共形形成的多晶硅层。 FinFET包括在多晶硅层上形成的金属栅极电极层。 本公开提供了制造FinFET的方法。 该方法包括提供包含半导体材料的翅片结构。 该方法包括在鳍结构上方形成栅极电介质层，栅介质层至少部分地围绕翅片结构缠绕。 该方法包括在栅介质层上形成多晶硅层，其中多晶硅层以保形方式形成。 该方法包括在多晶硅层上形成伪栅极层。

公开(公告)号：US09054130B2

公开(公告)日：2015-06-09

申请号：US12841763

申请日：2010-07-22

Applicant: Eric Peng ,  Chao-Cheng Chen ,  Ming-Hua Yu ,  Ying Hao Hsieh ,  Tze-Liang Lee ,  Chii-Horng Li ,  Syun-Ming Jang ,  Shih-Hao Lo

Inventor： Eric Peng ,  Chao-Cheng Chen ,  Ming-Hua Yu ,  Ying Hao Hsieh ,  Tze-Liang Lee ,  Chii-Horng Li ,  Syun-Ming Jang ,  Shih-Hao Lo

IPC: H01L21/302 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/66636

Abstract: The present disclosure provides a method for fabricating a semiconductor device that includes providing a silicon substrate, forming a gate stack over the silicon substrate, performing a biased dry etching process to the substrate to remove a portion of the silicon substrate, thereby forming a recess region in the silicon substrate, performing a non-biased etching process to the recess region in the silicon substrate, thereby forming a bottle-neck shaped recess region in the silicon substrate, and epi-growing a semiconductor material in the bottle-neck shaped recess region in the silicon substrate. An embodiment may include a biased dry etching process including adding HeO2 gas and HBr gas. An embodiment may include performing a first biased dry etching process including N2 gas and performing a second biased dry etching process not including N2 gas. An embodiment may include performing an oxidation process to the recess region in the silicon substrate by adding oxygen gas to form silicon oxide on a portion of the recess region in the silicon substrate. As such, these processes form polymer protection to help form the bottle-neck shaped recess.

Abstract translation: 本公开提供了一种制造半导体器件的方法，其包括提供硅衬底，在硅衬底上形成栅极堆叠，对衬底执行偏置的干蚀刻工艺以去除硅衬底的一部分，从而形成凹陷区域 在硅衬底中，对硅衬底中的凹陷区域进行非偏置蚀刻工艺，从而在硅衬底中形成瓶颈形凹部区域，并且在瓶颈形凹部区域中生长半导体材料 在硅衬底中。 一个实施例可以包括偏置的干蚀刻工艺，包括加入HeO2气体和HBr气体。 实施例可以包括执行包括N 2气体的第一偏压干法蚀刻工艺，并执行不包括N 2气体的第二偏压干式蚀刻工艺。 一个实施例可以包括通过在硅衬底中的一部分凹陷区域上添加氧气以形成氧化硅，来对硅衬底中的凹陷区域进行氧化处理。 因此，这些方法形成聚合物保护以帮助形成瓶颈形凹部。