公开(公告)号：US07008868B2

公开(公告)日：2006-03-07

申请号：US10818647

申请日：2004-04-05

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L21/44 ,  H01L21/4763

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/03831 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05572 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166

Abstract: A bumped wafer for use in making a chip device. The bumped wafer includes two titanium layers sputtered alternatingly with two copper layers over a non-passivated die. The bumped wafer further includes under bump material under solder bumps contained thereon.

公开(公告)号：US20050285238A1

公开(公告)日：2005-12-29

申请号：US10876248

申请日：2004-06-24

Applicant: Rajeev Joshi ,  Jonathan Noquil ,  Consuelo Tangpuz

Inventor： Rajeev Joshi ,  Jonathan Noquil ,  Consuelo Tangpuz

IPC: H01L21/335 ,  H01L23/00 ,  H01L23/495 ,  H01L25/07 ,  H02M3/00

CPC classification number: H01L23/562 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/97 ,  H01L25/072 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H02M3/00 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

Abstract: An integrated transistor module includes a lead frame that defines at least one low-side land and at least one high-side land. A stepped portion of the lead frame mechanically and electrically interconnects the low-side and high-side lands. A low-side transistor is mounted upon the low-side land with its drain electrically connected to the low-side land. A high-side transistor is mounted upon the high-side land with its source electrically connected to the high-side land.

Abstract translation: 集成晶体管模块包括限定至少一个低侧焊盘和至少一个高侧焊盘的引线框架。 引线框架的台阶部分将低边和高边平台机械地和电气地互连。 低侧晶体管安装在低侧焊盘上，其漏极电连接到低侧焊盘。 高侧晶体管安装在高侧焊盘上，其源极与高侧焊盘电连接。

公开(公告)号：US20050275089A1

公开(公告)日：2005-12-15

申请号：US10864909

申请日：2004-06-09

Applicant: Rajeev Joshi ,  Maria Estacio ,  David Chong ,  B. H. Gooi ,  Stephen Martin

Inventor： Rajeev Joshi ,  Maria Estacio ,  David Chong ,  B. H. Gooi ,  Stephen Martin

IPC: H01L21/48 ,  H01L23/24 ,  H01L23/31 ,  H01L23/34 ,  H01L23/433 ,  H01L23/495

CPC classification number: H01L23/4334 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49551 ,  H01L24/29 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/05647 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/73265 ,  H01L2224/83805 ,  H01L2224/85051 ,  H01L2224/85399 ,  H01L2224/85986 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/85186 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/4554

Abstract: An integrated circuit assembly includes a lead frame having a plurality of leads with inner portions. A thermally-conductive clip member is bonded to the inner portions of the leads such that the clip member is electrically isolated from and yet thermally coupled to the lead frame. An integrated circuit die is bonded and thereby thermally coupled to the clip member. The die is electrically connected to the wire die by wire bonds. Encapsulant material is disposed over the inner portions of the leads and at least a portion of the clip member, and encapsulates the die and the wire bonds.

Abstract translation: 集成电路组件包括具有多个具有内部部分的引线的引线框架。 导热夹构件结合到引线的内部，使得夹构件与引线框架电隔离并且热耦合到引线框架。 集成电路芯片被结合，从而热耦合到夹子构件。 模具通过引线键与导线管芯电连接。 封装材料设置在引线的内部部分和夹子构件的至少一部分上，并封装模具和引线接合。

公开(公告)号：US5789809A

公开(公告)日：1998-08-04

申请号：US517603

申请日：1995-08-22

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L21/60 ,  H01L23/31 ,  H01L23/12 ,  H01L23/10 ,  H01L23/34 ,  H01L23/48

CPC classification number: H01L24/81 ,  H01L23/3157 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/81801 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/16152

Abstract: An integrated circuit package includes a die and an electrically conductive cap attached to the top surface of the die. The die has a top surface, a bottom surface, an edge surface, a plurality of input/output terminals on the bottom surface of the die, and an input/output terminal pad on the top surface of the die. An electrically conductive arrangement is electrically connected to the input/output terminals on the bottom surface of the die providing an arrangement for electrically connecting the input/output terminals on the bottom surface of the die to other electrical elements. The electrically conductive cap attached to the top surface of the die provides an arrangement for electrically connecting the input/output terminal on the top surface of the die to other electrical elements and may be used to provide improved heat dissipation from the die.

Abstract translation: 集成电路封装包括管芯和连接到管芯顶表面的导电帽。 模具具有顶表面，底表面，边缘表面，在模具的底表面上的多个输入/输出端子，以及在模具顶表面上的输入/输出端子垫。 导电布置电连接到管芯的底表面上的输入/输出端子，提供用于将管芯底表面上的输入/输出端子电连接到其他电气元件的装置。 连接到管芯的顶表面的导电帽提供了用于将管芯顶表面上的输入/输出端子电连接到其它电气元件的布置，并且可以用于提供来自管芯的改进的散热。

公开(公告)号：US5637916A

公开(公告)日：1997-06-10

申请号：US596434

申请日：1996-02-02

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L21/48 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H05K3/00 ,  H05K3/40 ,  H01L23/495

CPC classification number: H01L24/97 ,  H01L21/486 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49838 ,  H01L24/49 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/181 ,  H05K3/0097 ,  H05K3/403 ,  Y10T29/49144 ,  Y10T29/49789 ,  Y10T29/49799

Abstract: The present invention discloses the use of a dielectric substrate panel suitable for supporting a plurality of independently packaged ICs. The substrate panel has a plurality of conductive landings arranged on its top surface, a plurality of conductive contacts arranged on its bottom surface and a multiplicity of electrically conductive vias. The vias pass through the substrate panel and are arranged to interconnect selected landings with their associated conductive contacts. The top surface of the substrate panel also includes a number of die attach areas. During packaging, dies are secured to their associated die attach areas on the substrate panel and electrically coupled to appropriate conductive landings. An encapsulant is then formed over each of the dies for protection.

Abstract translation: 本发明公开了适用于支持多个独立封装的IC的电介质基板的使用。 衬底面板具有布置在其顶表面上的多个导电平台，布置在其底表面上的多个导电触头和多个导电通孔。 通孔穿过衬底面板并且布置成将选定的平台与其相关联的导电触点相互连接。 衬底面板的顶表面还包括多个管芯附接区域。 在包装期间，管芯被固定到其相关的管芯附着区域在基板面板上并且电耦合到适当的导电平台。 然后在每个模具上形成密封剂用于保护。

公开(公告)号：US09053853B1

公开(公告)日：2015-06-09

申请号：US13684452

申请日：2012-11-23

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01F7/06 ,  H01F41/00

CPC classification number: H01F41/00 ,  H01F27/2804 ,  H01F27/29 ,  H01F2027/2809 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Embodiments of the present invention relate to a method of forming a magnetics package. The method includes providing a primary coil configured to conduct a current flow; providing a substrate having a surface and a secondary coil extending from the surface, the secondary coil configured to conduct a current flow; encapsulating the secondary coil in a secondary mold compound; removing the substrate from the secondary coil, thereby leaving the secondary coil embedded in the secondary mold compound; and inductively coupling the secondary coil to the primary coil through a magnetic core, the secondary coil is electrically isolated from the primary coil, wherein a current flow in the primary coil produces a magnetic field in the magnetic core, and the magnetic field in the magnetic core induces a current flow in the secondary coil.

Abstract translation: 本发明的实施例涉及一种形成磁性封装的方法。 该方法包括提供构造成传导电流的初级线圈; 提供具有表面的基板和从表面延伸的次级线圈，所述次级线圈构造成导通电流; 将次级线圈封装在二次模具化合物中; 从次级线圈移除基板，从而使次级线圈嵌入在二次模具化合物中; 并且通过磁芯将次级线圈感应耦合到初级线圈，次级线圈与初级线圈电隔离，其中初级线圈中的电流在磁芯中产生磁场，并且磁场中的磁场 芯在次级线圈中感应出电流。

公开(公告)号：US08609978B2

公开(公告)日：2013-12-17

申请号：US12069094

申请日：2008-02-06

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L31/042

CPC classification number: H01L31/044 ,  H01L31/052 ,  H01L31/0521 ,  H01L31/054 ,  H01L31/0543 ,  Y02E10/52 ,  Y10T29/49002

Abstract: A leadframe based photovoltaic assembly and method for assembling the same is disclosed. The photovoltaic assembly comprises a first and second mold compounds to effectuate the accurate placement of an optical concentrator above a photovoltaic cell. The photovoltaic assembly is able to be assembled using existing mature semiconductor packaging technologies.

Abstract translation: 公开了一种基于引线框的光伏组件及其组装方法。 光伏组件包括第一和第二模具化合物，以实现光聚焦器在光伏电池上方的精确放置。 光伏组件能够使用现有的成熟半导体封装技术进行组装。

公开(公告)号：US08524532B1

公开(公告)日：2013-09-03

申请号：US13406257

申请日：2012-02-27

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L21/00

CPC classification number: H01L27/088 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/96 ,  H01L27/0629 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2518 ,  H01L2924/12042 ,  H01L2924/1306 ,  H05K1/186 ,  H05K3/4661 ,  H01L2924/00

Abstract: One aspect of the invention pertains to an integrated circuit package with an embedded power stage. The integrated circuit package includes a first field effect transistor (FET) and a second FET that are electrically coupled with one another. The FETs are embedded in a dielectric substrate that is formed from multiple dielectric layers. The dielectric layers are laminated together with one or more foil layers that help form an electrical interconnect for the package. Various embodiments relate to method of forming the above package.

Abstract translation: 本发明的一个方面涉及具有嵌入式功率级的集成电路封装。 集成电路封装包括彼此电耦合的第一场效应晶体管（FET）和第二FET。 FET被嵌入在由多个电介质层形成的电介质基板中。 电介质层与一个或多个箔层压在一起，这些箔层有助于形成用于封装的电互连。 各种实施例涉及形成上述包装的方法。

公开(公告)号：US20120064667A1

公开(公告)日：2012-03-15

申请号：US13297938

申请日：2011-11-16

Applicant: Rajeev Joshi ,  Venkat Iyer ,  Jonathan Klein

Inventor： Rajeev Joshi ,  Venkat Iyer ,  Jonathan Klein

IPC: H01L21/50

CPC classification number: H01L23/49575 ,  H01L23/492 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73253 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor die package capable of being mounted to a motherboard is disclosed. The semiconductor die package includes a substrate, and a first semiconductor die mounted on the substrate, where the first semiconductor die includes a first vertical device comprising a first input region and a first output region at opposite surfaces of the first semiconductor die. The semiconductor die package includes a second semiconductor die mounted on the substrate, where second semiconductor die comprises a second vertical device comprising a second input region and a second output region at opposite surfaces of the second semiconductor die. A substantially planar conductive node clip electrically communicates the first output region in the first semiconductor die and the second input region in the second semiconductor die. The first semiconductor die and the second semiconductor die are between the substrate and the conductive node clip.

Abstract translation: 公开了一种能够安装在母板上的半导体管芯封装。 半导体管芯封装包括衬底和安装在衬底上的第一半导体管芯，其中第一半导体管芯包括第一垂直器件，第一垂直器件包括第一半导体管芯的相对表面处的第一输入区域和第一输出区域。 半导体管芯封装包括安装在基板上的第二半导体管芯，其中第二半导体管芯包括第二垂直器件，该第二垂直器件包括在第二半导体管芯的相对表面处的第二输入区域和第二输出区域。 基本上平面的导电节点夹将第一半导体管芯中的第一输出区域和第二半导体管芯中的第二输入区域电连通。 第一半导体管芯和第二半导体管芯位于衬底和导电节点夹之间。

公开(公告)号：US07582956B2

公开(公告)日：2009-09-01

申请号：US11693141

申请日：2007-03-29

Applicant: Rajeev Joshi ,  Consuelo N. Tangpuz ,  Romel N. Manatad

Inventor： Rajeev Joshi ,  Consuelo N. Tangpuz ,  Romel N. Manatad

IPC: H01L23/495

CPC classification number: H01L23/49562 ,  H01L23/3121 ,  H01L23/3185 ,  H01L23/49531 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.

Abstract translation: 一种芯片器件，包括引线框架，模具和模具化合物。 模具的背面被金属化并且通过在模具化合物中限定的窗口暴露，当模具化合物耦合到引线框架时封装模具。 引线框架上的引线耦合到管芯上的源极和栅极端子，而管芯的金属化背面用作漏极端子。