公开(公告)号：US09936572B2

公开(公告)日：2018-04-03

申请号：US14793447

申请日：2015-07-07

Applicant: Dell Products L.P.

Inventor： Umesh Chandra ,  Henry M. Wolst

IPC: H05K7/00 ,  H05K1/02 ,  H01B7/08 ,  H02G3/04 ,  H05K1/11 ,  H05K3/34

CPC classification number: H05K1/025 ,  H05K1/0245 ,  H05K1/111 ,  H05K3/341 ,  H05K2201/09227 ,  H05K2201/09727 ,  H05K2201/10189

Abstract: A differential trace pair system includes a board having a first board structure member and a second board structure member. A differential trace pair in the board includes a first differential trace pair portion of a first width outside the board structure, and a second differential trace pair portion of a second width extending through the board structure. A first outer edge and a second outer edge of the second differential trace pair portion define the second width that is less than the first width. A first board structure member channel is defined by the first outer edge adjacent the first board structure member, a second board structure member channel is defined by the second outer edge adjacent the second board structure member and the first and second board structure member channels provide a third width of the second differential trace pair portion that is less than the second width.

公开(公告)号：US11672077B2

公开(公告)日：2023-06-06

申请号：US17158524

申请日：2021-01-26

Applicant: Dell Products L.P.

Inventor： Umesh Chandra

IPC: H03H7/38 ,  H05K1/02

CPC classification number: H05K1/024 ,  H05K1/0245

Abstract: A zoned dielectric loss circuit board system includes a board. A first differential trace is included in the board. A dielectric layer is included the board and that includes a first dielectric layer zone that engages the first differential trace and that includes first dielectric loss characteristics, and a second dielectric layer zone that is located immediately adjacent the first dielectric layer zone and that includes second dielectric loss characteristics that are greater than the first dielectric loss characteristics. A second differential trace may be included in the board in engagement with the second dielectric layer zone, and may have a second trace length that is shorter than a first trace length of the first differential trace.

公开(公告)号：US11656264B2

公开(公告)日：2023-05-23

申请号：US17374119

申请日：2021-07-13

Applicant: Dell Products L.P.

Inventor： Umesh Chandra ,  Bhyrav Mutnury

IPC: G01R31/11 ,  G01R31/08 ,  G06F17/14 ,  G01M11/00 ,  G01R31/68

CPC classification number: G01R31/11 ,  G01M11/3109 ,  G01R31/083 ,  G01R31/68 ,  G06F17/142

Abstract: A high-speed signal subsystem testing system includes a processing system having a transmitter and a receiver, a loop back subsystem coupled to the transmitter and receiver to provide a testing communication path between the transmitter and the receiver, and a communication path testing engine coupled to the transmitter and the receiver. The communication path testing engine generates test signal(s) and transmits the test signal(s) via the transmitter and through the testing communication path provided by the loop back subsystem and, in response, receives test signal result(s) via the receiver and through the testing communication path provided by the loop back subsystem, The communication path testing engine processes the test signal result(s) to generate a testing impedance profile for the testing communication path, and compares the testing impedance profile to an expected impedance profile to determine whether a testing communication path issue exists in the testing communication path.

公开(公告)号：US20230018015A1

公开(公告)日：2023-01-19

申请号：US17374119

申请日：2021-07-13

Applicant: Dell Products L.P.

Inventor： Umesh Chandra ,  Bhyrav Mutnury

IPC: G01R31/11 ,  G01R31/08 ,  G01R31/68 ,  G01M11/00 ,  G06F17/14

Abstract: A high-speed signal subsystem testing system includes a processing system having a transmitter and a receiver, a loop back subsystem coupled to the transmitter and receiver to provide a testing communication path between the transmitter and the receiver, and a communication path testing engine coupled to the transmitter and the receiver. The communication path testing engine generates test signal(s) and transmits the test signal(s) via the transmitter and through the testing communication path provided by the loop back subsystem and, in response, receives test signal result(s) via the receiver and through the testing communication path provided by the loop back subsystem, The communication path testing engine processes the test signal result(s) to generate a testing impedance profile for the testing communication path, and compares the testing impedance profile to an expected impedance profile to determine whether a testing communication path issue exists in the testing communication path.

公开(公告)号：US20220390527A1

公开(公告)日：2022-12-08

申请号：US17336659

申请日：2021-06-02

Applicant: Dell Products L.P.

Inventor： Umesh Chandra ,  Bhyrav Mutnury

IPC: G01R31/58

Abstract: A high-speed signal subsystem testing system tests a processor transmitter and receiver coupled to a connector via a transmitter trace and a receiver trace, respectively. A transmitter test circuit on a testing board coupled to the connector compares a transmitter voltage received from the transmitter via the transmitter trace and the connector to a common mode voltage range and, in response to the transmitter voltage being outside the common mode voltage range, provides a transmitter trace issue signal. A receiver test circuit on the testing board coupled to the connector transmits a first test voltage towards the receiver, compares a second test voltage detected at the receiver test circuit in response to transmitting the first test voltage towards the receiver to a reference test voltage and, in response to the second test voltage being above the reference test voltage, provides a receiver trace issue signal.

公开(公告)号：US11490504B2

公开(公告)日：2022-11-01

申请号：US17384675

申请日：2021-07-23

Applicant: DELL PRODUCTS L.P.

Inventor： Umesh Chandra

IPC: H05K1/11 ,  H05K1/02

Abstract: A high-speed transmission circuit design reduces or eliminates the presence of unwanted stub-effects and avoids uncontrolled line impedances that in existing circuits cause impedance mismatches that give rise to unwanted reflections and, ultimately, degrade signal integrity, e.g., in belly-to-belly configurations involving Quad Small Form-Factor Pluggable Double Density (QSFP DD) connectors. In various embodiments, by preventing overcrowding of signal lines, the circuit design further reduces crosstalk and increases signal integrity.

公开(公告)号：US20200092986A1

公开(公告)日：2020-03-19

申请号：US16687408

申请日：2019-11-18

Applicant: Dell Products L.P.

Inventor： Umesh Chandra ,  Bhyrav M. Mutnury ,  Chun-Lin Liao

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11

Abstract: A differential trace pair system includes a board having a first, a second, a third, and a fourth board structure member. A differential trace pair in the board includes a first differential trace extending between the first and the third board structure members, and a second differential trace extending between the second and the fourth board structure members. The differential trace pair includes a serpentine region that includes a first portion and a second portion where the first and the second differential traces have a first width, are substantially parallel, and spaced apart by a first differential trace pair spacing, and a third portion in which the second differential trace includes a second width that is greater than the first width, the first and second differential traces are substantially parallel and spaced apart by a second differential trace pair spacing that is greater than the first differential trace pair spacing.

公开(公告)号：US10485096B2

公开(公告)日：2019-11-19

申请号：US15825746

申请日：2017-11-29

Applicant: Dell Products L.P.

Inventor： Umesh Chandra ,  Bhyrav M. Mutnury ,  Chun-Lin Liao

IPC: H05K1/00 ,  H05K1/02 ,  H05K1/11 ,  H05K1/16 ,  G06F17/00 ,  G06F17/50 ,  H04B3/32 ,  H04B3/50 ,  H04L25/02 ,  H05K1/18 ,  H05K3/10 ,  H05K3/06

Abstract: A differential trace pair system includes a board having a first, a second, a third, and a fourth board structure member. A differential trace pair in the board includes a first differential trace extending between the first and the third board structure members, and a second differential trace extending between the second and the fourth board structure members. The differential trace pair includes a serpentine region that includes a first portion and a second portion where the first and the second differential traces have a first width, are substantially parallel, and spaced apart by a first differential trace pair spacing, and a third portion in which the second differential trace includes a second width that is greater than the first width, the first and second differential traces are substantially parallel and spaced apart by a second differential trace pair spacing that is greater than the first differential trace pair spacing.

公开(公告)号：US20190239339A1

公开(公告)日：2019-08-01

申请号：US15885337

申请日：2018-01-31

Applicant: Dell Products L.P.

Inventor： Umesh Chandra ,  Bhyrav M. Mutnury ,  Mallikarjun Vasa

IPC: H05K1/02 ,  H04L25/02 ,  H04B3/32

CPC classification number: H05K1/0228 ,  H04B3/32 ,  H04L25/0272 ,  H05K2201/09227

Abstract: A stubbed differential trace pair system includes a circuit board having a first differential trace pair with a first trace and a second trace, and a second differential trace pair with a third trace and a fourth trace, where the first trace located opposite the second trace and the third trace from the fourth trace. Second trace stubs extend in a spaced apart orientation relative to each other and from a side of the second trace that is opposite the second trace from the first trace. Third trace stubs extend in a spaced apart orientation relative to each other and from a side of the third trace that is opposite the third trace from the fourth trace. The second trace stubs and the third trace stubs are configured to reduce crosstalk generated by the transmission of signals through the first differential trace pair and the second differential trace pair.

公开(公告)号：US20190166687A1

公开(公告)日：2019-05-30

申请号：US15825746

申请日：2017-11-29

Applicant: Dell Products L.P.

Inventor： Umesh Chandra ,  Bhyrav M. Mutnury ,  Chun-Lin Liao

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18

Abstract: A differential trace pair system includes a board having a first, a second, a third, and a fourth board structure member. A differential trace pair in the board includes a first differential trace extending between the first and the third board structure members, and a second differential trace extending between the second and the fourth board structure members. The differential trace pair includes a serpentine region that includes a first portion and a second portion where the first and the second differential traces have a first width, are substantially parallel, and spaced apart by a first differential trace pair spacing, and a third portion in which the second differential trace includes a second width that is greater than the first width, the first and second differential traces are substantially parallel and spaced apart by a second differential trace pair spacing that is greater than the first differential trace pair spacing.