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    BIPOLAR TRANSISTORS
    34.
    发明申请
    BIPOLAR TRANSISTORS 有权

    公开(公告)号：US20230087058A1

    公开(公告)日：2023-03-23

    申请号：US17549013

    申请日：2021-12-13

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Shesh Mani Pandey ,  Judson R. Holt ,  Vibhor Jain

    IPC: H01L29/732 ,  H01L29/66

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: a base region composed of a semiconductor on insulator material; an emitter region above the base region; and a collector region under the base region and within a cavity of a buried insulator layer.

    EPI SEMICONDUCTOR STRUCTURES WITH INCREASED EPI VOLUME IN SOURCE/DRAIN REGIONS OF A TRANSISTOR DEVICE FORMED ON AN SOI SUBSTRATE
    35.
    发明申请
    EPI SEMICONDUCTOR STRUCTURES WITH INCREASED EPI VOLUME IN SOURCE/DRAIN REGIONS OF A TRANSISTOR DEVICE FORMED ON AN SOI SUBSTRATE 有权

    公开(公告)号：US20220181468A1

    公开(公告)日：2022-06-09

    申请号：US17116167

    申请日：2020-12-09

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Shesh Mani Pandey ,  Judson Robert Holt

    IPC: H01L29/66 ,  H01L27/12 ,  H01L29/78

    Abstract: A transistor device formed on a semiconductor-on-insulator (SOI) substrate including a bulk semiconductor layer, a buried insulation (BOX) layer positioned on the bulk semiconductor layer, and an active semiconductor layer positioned on the BOX layer. The transistor device includes: a gate structure, a sidewall spacer, and a source/drain region; a plurality of distinct openings extending through the active semiconductor layer of the SOI substrate in the source/drain region adjacent the sidewall spacer, each opening of the plurality of openings extending to a respective recess formed in the BOX layer of the SOI substrate in the source/drain region adjacent the sidewall space, wherein each recess extends under a portion of the active semiconductor layer; and an epitaxial (epi) semiconductor material disposed in the recesses in the BOX layer, in the plurality of openings through the active semiconductor layer, and over a surface of the active semiconductor layer.

    CONCURRENT MANUFACTURE OF FIELD EFFECT TRANSISTORS AND BIPOLAR JUNCTION TRANSISTORS WITH GAIN TUNING
    37.
    发明申请
    CONCURRENT MANUFACTURE OF FIELD EFFECT TRANSISTORS AND BIPOLAR JUNCTION TRANSISTORS WITH GAIN TUNING 有权

    公开(公告)号：US20210193526A1

    公开(公告)日：2021-06-24

    申请号：US16720084

    申请日：2019-12-19

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Shesh Mani Pandey

    IPC: H01L21/8249 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/265 ,  H01L21/266 ,  H01L21/74

    Abstract: Bipolar junction transistors include a collector, a base on the collector, and an emitter on the base. The base is between the collector and the emitter. The emitter comprises first portions and a second portion on the base. The first portions of the emitter are between the second portion of the emitter and the base. The first portions and the second portion comprise doped areas that are doped with the same polarity impurity in different concentrations. The base comprises a doped area that is doped with an opposite polarity impurity from the first and second portions of the emitter. The first portions of the emitter extend from the second portion of the emitter into the base. Specifically, the second portion has a bottom surface contacting the base, and the first portions comprise at least two separate impurity regions extending from the bottom surface of the second portion into the base.

    Bipolar transistor and gate structure on semiconductor fin and methods to form same
    38.
    发明授权
    Bipolar transistor and gate structure on semiconductor fin and methods to form same 有权

    公开(公告)号：US12176427B2

    公开(公告)日：2024-12-24

    申请号：US17931938

    申请日：2022-09-14

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Shesh Mani Pandey ,  Vibhor Jain

    IPC: H01L29/735 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

    Abstract: Embodiments of the disclosure provide a bipolar transistor and gate structure on a semiconductor fin and methods to form the same. A structure according to the disclosure includes a semiconductor fin including an intrinsic base region and an extrinsic base region adjacent the intrinsic base region along a length of the semiconductor fin. Sidewalls of the intrinsic base region of the semiconductor fin are adjacent an emitter and a collector along a width of the semiconductor fin. A gate structure is on the semiconductor fin and between the intrinsic base region and the extrinsic base region.

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