公开(公告)号：US20250157529A1

公开(公告)日：2025-05-15

申请号：US18509519

申请日：2023-11-15

Applicant: GlobalFoundries U.S. Inc.

Inventor： Navneet K. Jain ,  Mahbub Rashed

IPC: G11C11/419

Abstract: A disclosed memory structure includes memory cells connected to first and second cell supply voltage lines. A programming circuit enables programming of a low cell supply voltage (Vcsl) on the first cell supply voltage line and includes transistors with different threshold voltages connected to ground and further connectable, via switches, to the first cell supply voltage line. The programming circuit can further include an additional switch connected between ground and the first cell supply voltage line. In an operational mode, the first cell supply voltage line is discharged to ground via the additional switch. In the retention mode, one of the transistors of the programming circuit is connected by a corresponding switch to the first cell supply voltage line for programming of Vcsl. Optionally, the memory structure can be implemented in FDSOI and the transistors of the programming circuit can also be back biased for fine tuning of Vcsl.

公开(公告)号：US11862240B2

公开(公告)日：2024-01-02

申请号：US17658189

申请日：2022-04-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vivek Raj ,  Shivraj Gurpadappa Dharne ,  Mahbub Rashed

IPC: G11C16/10 ,  G11C11/419 ,  H03K3/356 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412 ,  H03K3/356026 ,  H03K3/356078

Abstract: Embodiments of the disclosure provide a circuit structure and related method to provide a radiation resistant memory cell. A circuit structure may include a first latch having an input node and an output node. A second latch has an input node and an output node, in which the output node of the second latch is coupled to the input node of the first latch, and the input node of the second latch is coupled to the output node of the first latch. A read/write (R/W) circuit includes a plurality of transistors coupling a word line, a bit line, and an inverted bit line to at least two outputs. One of the at least two outputs is coupled to the input node of the first latch and another of the outputs is coupled to the input node of the second latch.