公开(公告)号：US20230197525A1

公开(公告)日：2023-06-22

申请号：US18067954

申请日：2022-12-19

Applicant: IMEC VZW

Inventor： Basoene Briggs ,  Boon Teik Chan ,  Juergen Boemmels

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/775 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/823807 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/775 ,  H01L21/02603 ,  H01L21/02532 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823878 ,  H01L29/66545 ,  H01L29/66439

Abstract: A method for forming a semiconductor device structure includes forming a layer stack comprising alternating sacrificial layers of a first semiconductor material and channel layers of a second semiconductor material. The method includes forming over the layer stack a plurality of parallel and regularly spaced core lines and forming spacer lines on side surfaces of the core lines. The method includes forming first trenches extending through the layer stack by etching the layer stack while using the core lines and the spacer lines as an etch mask and forming insulating walls in the first trenches and in the gaps by filling the first trenches and the gaps with insulating wall material. The method also includes forming second trenches extending through the layer stack by etching the layer stack while using the spacer lines and the insulating walls as an etch mask, thereby forming a plurality of pairs of fin structures.

公开(公告)号：US11682591B2

公开(公告)日：2023-06-20

申请号：US17409964

申请日：2021-08-24

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Juergen Boemmels ,  Basoene Briggs

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/775 ,  H01L21/762 ,  H01L21/8238

CPC classification number: H01L21/84 ,  H01L21/76283 ,  H01L27/1203 ,  H01L29/775 ,  H01L21/823878

Abstract: According to an aspect of the present inventive concept there is provided a method for forming a first and a second transistor structure, wherein the first and second transistor structures are spaced apart by an insulating wall, and the method comprising:



forming on a semiconductor layer of the substrate a first semiconductor layer stack and a second semiconductor layer stack, each layer stack comprising in a bottom-up direction a sacrificial layer and a channel layer, wherein the layer stacks are spaced apart by a trench extending into the semiconductor layer substrate, the trench being filled with an insulating wall material to form the insulating wall; and
processing the layer stacks to form the first and second transistor structures in the first and second device regions, respectively, the processing comprising forming source and drain regions and forming gate stacks;
the method further comprising, prior to said processing:
by etching removing the sacrificial layer of each layer stack to form a respective cavity on either sides of the insulating wall underneath the channel layer of the first and second layer stack, the channel layers being supported by the insulating wall; and
depositing a bottom insulating material in said cavities;

wherein, subsequent to said processing, the bottom insulating material forms a bottom insulating layer underneath the source region, the drain region and the channel regions on either side of the insulating wall.

公开(公告)号：US11462443B2

公开(公告)日：2022-10-04

申请号：US17110604

申请日：2020-12-03

Applicant: IMEC vzw

Inventor： Eugenio Dentoni Litta ,  Juergen Boemmels ,  Julien Ryckaert ,  Naoto Horiguchi ,  Pieter Weckx

IPC: H01L21/8238 ,  H01L27/092 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66

Abstract: In one aspect, a method of forming a semiconductor device, can comprise forming a first transistor structure and a second transistor structure separated by a trench. The first and the second transistor structures can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. A first and a second spacer can beformed in the trench at sidewalls of the transistor structures, both protruding above a top surface of the transistor structures. The method can comprise applying a first mask layer including an opening exposing the first spacer at a first source/drain portion of the first transistor structure and covering the second spacer, partially etching the exposed first spacer through the opening, exposing at least parts of a sidewall of the first source/drain portion of the first transistor structure, and removing the mask layer. The method can further comprise depositing a contact material over the transistor structures and the first and second spacer, filling the trench and contacting the first source/drain portion of the first transistor structure, and etching back the contact material layer below a top surface of the second spacer.

公开(公告)号：US20220068725A1

公开(公告)日：2022-03-03

申请号：US17409964

申请日：2021-08-24

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Juergen Boemmels ,  Basoene Briggs

IPC: H01L21/84 ,  H01L21/762 ,  H01L27/12

Abstract: According to an aspect of the present inventive concept there is provided a method for forming a first and a second transistor structure, wherein the first and second transistor structures are spaced apart by an insulating wall, and the method comprising:
forming on a semiconductor layer of the substrate a first semiconductor layer stack and a second semiconductor layer stack, each layer stack comprising in a bottom-up direction a sacrificial layer and a channel layer, wherein the layer stacks are spaced apart by a trench extending into the semiconductor layer substrate, the trench being filled with an insulating wall material to form the insulating wall; and
processing the layer stacks to form the first and second transistor structures in the first and second device regions, respectively, the processing comprising forming source and drain regions and forming gate stacks;
the method further comprising, prior to said processing:
by etching removing the sacrificial layer of each layer stack to form a respective cavity on either sides of the insulating wall underneath the channel layer of the first and second layer stack, the channel layers being supported by the insulating wall; and
depositing a bottom insulating material in said cavities;
wherein, subsequent to said processing, the bottom insulating material forms a bottom insulating layer underneath the source region, the drain region and the channel regions on either side of the insulating wall.

公开(公告)号：US11257823B2

公开(公告)日：2022-02-22

申请号：US16049528

申请日：2018-07-30

Applicant: IMEC vzw

Inventor： Juergen Boemmels

IPC: H01L27/11 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L21/265 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/36 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/027 ,  H01L21/28 ,  H01L21/306 ,  H01L21/321 ,  H01L21/3213 ,  H01L29/49

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to a static random access memory (SRAM) having vertical channel transistors and methods of forming the same. In an aspect, a semiconductor device includes a semiconductor substrate and a semiconductor bottom electrode region formed on the substrate and including a first region, a second region and a third region arranged side-by-side. The second region is arranged between the first and the third regions. A first vertical channel transistor, a second vertical channel transistor and a third vertical channel transistor are arranged on the first region, the second region and the third region, respectively. The first, second and third regions are doped such that a first p-n junction is formed between the first and the second regions and a second p-n junction is formed between the second and third regions. A connection region is formed in the bottom electrode region underneath the first, second and third regions, wherein the connection region and the first and third regions are doped with a dopant of a same type. A resistance of a path extending between the first and the third regions through the connection region is lower than a resistance of a path extending between the first and the third regions through the second region. A second aspect is a method of forming the semiconductor device of the first aspect.

公开(公告)号：US10395978B2

公开(公告)日：2019-08-27

申请号：US15907118

申请日：2018-02-27

Applicant: IMEC VZW

Inventor： Basoene Briggs ,  Farid Sebaai ,  Juergen Boemmels ,  Zsolt Tokei ,  Christopher Wilson ,  Katia Devriendt

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/308

Abstract: The disclosed technology generally relates to semiconductor processing, and more particularly to patterning a target layer using a sacrificial structure. According to an aspect of the disclosed technology, a method of patterning a target layer comprises forming on the target layer a plurality of parallel material lines spaced apart such that longitudinal gaps exposing the target layer are formed between the material lines. The method additionally includes filling the gaps with a sacrificial material and forming a hole by removing the sacrificial material along a portion of one of the gaps, where the hole extends across the gap. The hole exposes the target layer in the gap. The method additionally includes filling the hole with a fill material to form a block portion extending across the gap. The method additionally includes removing, selectively to the material lines and the block portion, the sacrificial material from the target layer to expose the gaps, where the one of the gaps is interrupted in the longitudinal direction by the block portion. The method further includes transferring a pattern including the material lines and the block portion into the target layer.

公开(公告)号：US20190229196A1

公开(公告)日：2019-07-25

申请号：US16253321

申请日：2019-01-22

Applicant: IMEC VZW ,  GLOBALFOUNDRIES INC.

Inventor： Syed Muhammad Yasser Sherazi ,  Julien Ryckaert ,  Juergen Boemmels ,  Guillaume Bouche

IPC: H01L29/417 ,  H01L21/768 ,  H01L23/522 ,  H01L21/311 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/41791 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/5226 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device includes: (i) a substrate; (ii) a first elongated semiconductor structure extending in a first horizontal direction along the substrate and protruding vertically above the substrate, wherein a first set of source/drain regions are formed on the first semiconductor structure; (iii) a second elongated semiconductor structure extending along the substrate in parallel to the first semiconductor structure and protruding vertically above the substrate, wherein a second set of source/drain regions are formed on the second semiconductor structure; and (iv) a first set of source/drain contacts formed on the first set of source/drain regions, wherein a first source/drain contact of the first set of source/drain contacts includes: (a) a vertically extending contact portion formed directly above a first source/drain region of the first set of source/drain regions, and (b) a via landing portion protruding horizontally from the vertically extending contact portion in a direction towards the second semiconductor structure.

公开(公告)号：US20180247863A1

公开(公告)日：2018-08-30

申请号：US15907118

申请日：2018-02-27

Applicant: IMEC VZW

Inventor： Basoene Briggs ,  Farid Sebaai ,  Juergen Boemmels ,  Zsolt Tokei ,  Christopher Wilson ,  Katia Devriendt

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139

Abstract: The disclosed technology generally relates to semiconductor processing, and more particularly to patterning a target layer using a sacrificial structure. According to an aspect of the disclosed technology, a method of patterning a target layer comprises forming on the target layer a plurality of parallel material lines spaced apart such that longitudinal gaps exposing the target layer are formed between the material lines. The method additionally includes filling the gaps with a sacrificial material and forming a hole by removing the sacrificial material along a portion of one of the gaps, where the hole extends across the gap. The hole exposes the target layer in the gap. The method additionally includes filling the hole with a fill material to form a block portion extending across the gap. The method additionally includes removing, selectively to the material lines and the block portion, the sacrificial material from the target layer to expose the gaps, where the one of the gaps is interrupted in the longitudinal direction by the block portion. The method further includes transferring a pattern including the material lines and the block portion into the target layer.

公开(公告)号：US09859161B2

公开(公告)日：2018-01-02

申请号：US15451175

申请日：2017-03-06

Applicant: IMEC vzw

Inventor： Juergen Boemmels ,  Zsolt Tokei ,  Christopher Wilson

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295

Abstract: An interconnect structure and a method for forming it is disclosed. In one aspect, the method includes the steps of providing a first entity. The first entity includes a first set of line structures. The first set of line structures include a first set of conductive lines, and a first set of dielectric lines made of a first dielectric material and aligned with and overlaying the first set of conductive lines. The first entity also includes gaps separating the line structures and filled with a second dielectric material of such a nature that the first dielectric material can be selectively etched with respect to the second dielectric material. The method also includes providing a patterned mask on the first entity. The method further includes etching selectively the first dielectric material through the patterned mask so as to form one or more vias in the first dielectric material. The method also includes removing the patterned mask.