公开(公告)号：US12087682B2

公开(公告)日：2024-09-10

申请号：US16907797

申请日：2020-06-22

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Georgios Dogiamis ,  Beomseok Choi ,  Henning Braunisch ,  William Lambert ,  Krishna Bharath ,  Johanna Swan

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/48 ,  H01L23/50 ,  H01L25/00 ,  H01L25/065 ,  H05K1/18

CPC classification number: H01L23/50 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/3185 ,  H01L23/367 ,  H01L23/481 ,  H01L23/562 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H05K1/181 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/18161

Abstract: An integrated circuit assembly may be fabricated having an electronic substrate, an integrated circuit device having a first surface, an opposing second surface, at least one side extending between the first surface and the second surface, and at least one through-substrate via extending into the integrated circuit device from the second surface, wherein the first surface of the integrated circuit device is electrically attached to the electronic substrate; and at least one power delivery route electrically attached to the second surface of the integrated circuit device and to the electronic substrate, wherein the at least one power delivery route is conformal to the side of the integrated circuit device and the first surface of the electronic substrate.

公开(公告)号：US20230096368A1

公开(公告)日：2023-03-30

申请号：US17485243

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Adel Elsherbini ,  Johanna Swan ,  Feras Eid ,  Thomas L. Sounart ,  Henning Braunisch ,  Beomseok Choi ,  Krishna Bharath ,  Kaladhar Radhakrishnan ,  William J. Lambert

IPC: H01L49/02 ,  H01F27/255 ,  H01F27/28 ,  H01F41/04 ,  H01F41/02 ,  H01L23/498 ,  H01L23/64 ,  H01L21/48

Abstract: An inductor structure, a package substrate, an integrated circuit device, an integrated circuit device assembly and a method of fabricating the inductor structure. The inductor structure includes: an electrically conductive body; and a magnetic structure including a non-electrically-conductive magnetic material, wherein: one of the magnetic structure or the electrically conductive body wraps around another one of the magnetic structure or the electrically conductive body to form the inductor structure therewith; and at least one of the electrically conductive body or the magnetic structure has a granular microstructure including randomly distributed particles presenting substantially non-linear particle-to-particle boundaries with one another.

公开(公告)号：US20230095063A1

公开(公告)日：2023-03-30

申请号：US17484286

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Beomseok Choi ,  William J. Lambert ,  Krishna Bharath ,  Kaladhar Radhakrishnan ,  Adel Elsherbini ,  Henning Braunisch ,  Stephen Morein ,  Aleksandar Aleksov ,  Feras Eid

IPC: G05F1/44 ,  H01L23/50 ,  H01L25/065

Abstract: In one embodiment, an apparatus includes a first die with voltage regulator circuitry and a second die with logic circuitry. The apparatus further includes an inductor, a capacitor, and a conformal power delivery structure on the top side of the apparatus, where the voltage regulator circuitry is connected to the logic circuitry through the inductor, the capacitor, and the conformal power delivery structure. The conformal power delivery structure includes a first electrically conductive layer defining one or more recesses, a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer, and a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.

公开(公告)号：US20220416393A1

公开(公告)日：2022-12-29

申请号：US17359138

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Johanna Swan ,  Adel Elsherbini ,  Shawna Liff ,  Beomseok Choi ,  Qiang Yu

IPC: H01P3/16 ,  H01L25/065 ,  H01P1/208 ,  H01L23/538 ,  H01P5/107 ,  H01L23/66

Abstract: Waveguide interconnects for semiconductor packages are disclosed. An example semiconductor package includes a first semiconductor die, a second semiconductor die, and a substrate positioned between the first and second dies. The substrate includes a waveguide interconnect to provide a communication channel to carry an electromagnetic signal. The waveguide interconnect is defined by a plurality of through substrate vias (TSVs). The TSVs in a pattern around the at least the portion of the substrate to define a boundary of the communication channel.

公开(公告)号：US20210407903A1

公开(公告)日：2021-12-30

申请号：US16914062

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Georgios Dogiamis ,  Henning Braunisch ,  Beomseok Choi ,  William J. Lambert ,  Stephen Morein ,  Ahmed Abou-Alfotouh ,  Johanna Swan

IPC: H01L23/522 ,  H01L23/532 ,  H05K1/11 ,  H05K3/14 ,  H01L21/768

Abstract: An integrated circuit (IC) die package substrate comprises a first trace upon, or embedded within, a dielectric material. The first trace comprises a first metal and a first via coupled to the first trace. The first via comprises the first metal and a second trace upon, or embedded within, the dielectric material. A second via is coupled to the second trace, and at least one of the second trace or the second via comprises a second metal with a different microstructure or composition than the first metal.