公开(公告)号：US20250112216A1

公开(公告)日：2025-04-03

申请号：US18478937

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Qiang Yu ,  Georgios C. Dogiamis ,  Said Rami ,  Adel Elsherbini

IPC: H01L25/18 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00

Abstract: Methods of selectively transferring integrated circuit (IC) components between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a release layer and a layer of IC components over the release layer is received, and a second substrate with one or more adhesive areas is received. The layer of IC components may include one or more thick gate oxide transistors, group III-V transistors, varactors, or electrostatic discharge protection devices. The first substrate is partially bonded to the second substrate, such that a subset of IC components on the first substrate are bonded to the adhesive areas on the second substrate. The first substrate is then separated from the second substrate, and the subset of IC components bonded to the second substrate are separated from the first substrate and remain on the second substrate.

公开(公告)号：US20220415555A1

公开(公告)日：2022-12-29

申请号：US17359165

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Qiang Yu ,  Adel Elsherbini ,  Kimin Jun

IPC: H01F27/06 ,  H01L23/64 ,  H01L23/522 ,  H01L23/528 ,  H01L49/02 ,  H01F27/28 ,  H01L21/50

Abstract: Methods and apparatus for inductor and transformer semiconductor devices using hybrid bonding technology are disclosed. An example semiconductor device includes a first standoff substrate; a second standoff substrate adjacent the first standoff substrate; and a conductive layer adjacent at least one of the first standoff substrate or the second standoff substrate.

公开(公告)号：US12266840B2

公开(公告)日：2025-04-01

申请号：US17359138

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Johanna Swan ,  Adel Elsherbini ,  Shawna Liff ,  Beomseok Choi ,  Qiang Yu

IPC: H01P3/16 ,  H01L23/538 ,  H01L23/66 ,  H01L25/065 ,  H01P1/208 ,  H01P5/107

Abstract: Waveguide interconnects for semiconductor packages are disclosed. An example semiconductor package includes a first semiconductor die, a second semiconductor die, and a substrate positioned between the first and second dies. The substrate includes a waveguide interconnect to provide a communication channel to carry an electromagnetic signal. The waveguide interconnect is defined by a plurality of through substrate vias (TSVs). The TSVs in a pattern around the at least the portion of the substrate to define a boundary of the communication channel.

公开(公告)号：US12300579B2

公开(公告)日：2025-05-13

申请号：US17346895

申请日：2021-06-14

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Qiang Yu ,  Feras Eid ,  Adel Elsherbini ,  Kimin Jun ,  Johanna Swan ,  Shawna Liff

IPC: H01L23/473 ,  H01L23/13 ,  H01L23/538 ,  H01L25/065 ,  H05K7/20 ,  H01L23/00

Abstract: An integrated circuit (IC) package may be fabricated having an interposer, one or more microfluidic channels through the interposer, a first IC chip attached to a first side of the interposer, and a second IC chip attached to a second side of the interposer, where the first side of the interposer includes first bond pads coupled to first bond pads of the first IC chip, and the second side of the interposer includes second bond pads coupled to first bond pads of the second IC chip. In an embodiment of the present description, a liquid cooled three-dimensional IC (3DIC) package may be formed with the IC package, where at least two IC devices may be stacked with a liquid cooled interposer. In a further embodiment, the liquid cooled 3DIC package may be electrically attached to an electronic board. Other embodiments are disclosed and claimed.

公开(公告)号：US20230299123A1

公开(公告)日：2023-09-21

申请号：US17698939

申请日：2022-03-18

Applicant: Intel Corporation

Inventor： Qiang Yu ,  Gwang-Soo Kim ,  Said Rami

IPC: H01L49/02 ,  H01L23/00 ,  H01L23/522 ,  H01L25/065

CPC classification number: H01L28/10 ,  H01L24/08 ,  H01L23/5227 ,  H01L24/06 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2224/08121 ,  H01L2224/06051 ,  H01L2224/0603 ,  H01L2224/0615 ,  H01L2224/0613 ,  H01L25/0652

Abstract: In one embodiment, an apparatus includes a first integrated circuit die with metal bonding pads that are co-planar with an external surface of the die and a second integrated circuit die with metal bonding pads that are co-planar with an external surface of the die. The first and second integrated circuit dies are coupled together such that their external surfaces are in contact and the metal pads of the first integrated circuit die are in direct contact with respective metal pads of the second integrated circuit die. The apparatus also includes an inductor formed at least partially by the metal pads of the first integrated circuit die and the metal pads of the second integrated circuit die.

公开(公告)号：US20220399249A1

公开(公告)日：2022-12-15

申请号：US17346895

申请日：2021-06-14

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Qiang Yu ,  Feras Eid ,  Adel Elsherbini ,  Kimin Jun ,  Johanna Swan ,  Shawna Liff

IPC: H01L23/473 ,  H01L23/13 ,  H01L23/538 ,  H05K7/20 ,  H01L25/065

Abstract: An integrated circuit (IC) package may be fabricated having an interposer, one or more microfluidic channels through the interposer, a first IC chip attached to a first side of the interposer, and a second IC chip attached to a second side of the interposer, where the first side of the interposer includes first bond pads coupled to first bond pads of the first IC chip, and the second side of the interposer includes second bond pads coupled to first bond pads of the second IC chip. In an embodiment of the present description, a liquid cooled three-dimensional IC (3DIC) package may be formed with the IC package, where at least two IC devices may be stacked with a liquid cooled interposer. In a further embodiment, the liquid cooled 3DIC package may be electrically attached to an electronic board. Other embodiments are disclosed and claimed.

公开(公告)号：US11515424B2

公开(公告)日：2022-11-29

申请号：US16270826

申请日：2019-02-08

Applicant: Intel Corporation

Inventor： Said Rami ,  Hyung-Jin Lee ,  Saurabh Morarka ,  Guannan Liu ,  Qiang Yu ,  Bernhard Sell ,  Mark Armstrong

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/49 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/40 ,  H01L29/08 ,  H01L21/265 ,  H01L29/165

Abstract: Disclosed herein are field-effect transistors with asymmetric gate stacks. An example transistor includes a channel material and an asymmetric gate stack, provided over a portion of the channel material between source and drain (S/D) regions. The gate stack is asymmetric in that a thickness of a gate dielectric of a portion of the gate stack closer to one of the S/D regions is different from that of a portion of the gate stack closer to the other S/D region, and in that a work function (WF) material of a portion of the gate stack closer to one of the S/D regions is different from a WF material of a portion of the gate stack closer to the other S/D region. Transistors as described herein exploit asymmetry in the gate stacks to improve the transistor performance in terms of high breakdown voltage, high gain, and/or high output resistance.

公开(公告)号：US20220399294A1

公开(公告)日：2022-12-15

申请号：US17347394

申请日：2021-06-14

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Qiang Yu ,  Adel A. Elsherbini ,  Shawna M. Liff

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die-level interposer having a first surface and an opposing second surface; a first die coupled to the first surface of the die-level interposer by a first hybrid bonding region having a first pitch; a second die coupled to the second surface of the die-level interposer by a second hybrid bonding region having a second pitch different from the first pitch; and a third die coupled to the second surface of the die-level interposer by a third hybrid bonding region having a third pitch different from the first and second pitches.

公开(公告)号：US20200259018A1

公开(公告)日：2020-08-13

申请号：US16270826

申请日：2019-02-08

Applicant: Intel Corporation

Inventor： Said Rami ,  Hyung-Jin Lee ,  Saurabh Morarka ,  Guannan Liu ,  Qiang Yu ,  Bernhard Sell ,  Mark Armstrong

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/49 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/40

Abstract: Disclosed herein are field-effect transistors with asymmetric gate stacks. An example transistor includes a channel material and an asymmetric gate stack, provided over a portion of the channel material between source and drain (S/D) regions. The gate stack is asymmetric in that a thickness of a gate dielectric of a portion of the gate stack closer to one of the S/D regions is different from that of a portion of the gate stack closer to the other S/D region, and in that a work function (WF) material of a portion of the gate stack closer to one of the S/D regions is different from a WF material of a portion of the gate stack closer to the other S/D region. Transistors as described herein exploit asymmetry in the gate stacks to improve the transistor performance in terms of high breakdown voltage, high gain, and/or high output resistance.

公开(公告)号：US20250112188A1

公开(公告)日：2025-04-03

申请号：US18478923

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Georgios C. Dogiamis ,  Qiang Yu ,  Adel Elsherbini ,  Tushar Kanti Talukdar ,  Thomas L. Sounart

IPC: H01L23/00 ,  H01L21/683 ,  H01L23/538 ,  H01L25/00 ,  H01L25/18

Abstract: Methods of selectively transferring integrated circuit (IC) components between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a release layer and a layer of IC components over the release layer is received, and a second substrate with one or more adhesive areas is received. The layer of IC components may include one or more antennas, interconnects, inductors, capacitors, or transformers. The first substrate is partially bonded to the second substrate, such that a subset of IC components on the first substrate are bonded to the adhesive areas on the second substrate. The first substrate is then separated from the second substrate, and the subset of IC components bonded to the second substrate are separated from the first substrate and remain on the second substrate.