公开(公告)号：US10790159B2

公开(公告)日：2020-09-29

申请号：US15920881

申请日：2018-03-14

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Chong Zhang ,  Yikang Deng ,  Junnan Zhao ,  Ying Wang

IPC: H01L21/48 ,  H01F27/28 ,  H01F41/24 ,  H01L21/67 ,  H01F17/00 ,  H01F41/04 ,  H01F17/06 ,  H05K1/16 ,  H05K3/00

Abstract: The systems and methods described herein provide for the fabrication of semiconductor package substrates having magnetic inductors formed in at least a portion of the through-holes formed in the semiconductor package substrate. Such magnetic inductors are formed without exposing the magnetic material disposed in the through-hole to any wet chemistry (desmear, electro-less plating, etc.) processes by sealing the magnetic material with a patterned sealant (e.g., patterned dry film resist) which seals the magnetic material prior to performing steps involving wet chemistry on the semiconductor package substrate. Such beneficially minimizes or even eliminates the contamination of wet chemistry reagents by the magnetic material should the magnetic material remain exposed during the wet chemistry processes. The patterned sealant is removed subsequent to the semiconductor package processing steps involving wet chemistry.

公开(公告)号：US20200211927A1

公开(公告)日：2020-07-02

申请号：US16233808

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Cheng Xu ,  Yikang Deng ,  Junnan Zhao ,  Ying Wang ,  Chong Zhang ,  Kyu Oh Lee ,  Chandra Mohan Jha ,  Chia-Pin Chiu

IPC: H01L23/473 ,  H01L21/48

Abstract: Microelectronic assemblies that include a cooling channel, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a surface, a die having a surface, and a fluidic channel between the surface of the die and the surface of the package substrate, wherein a top surface of the fluidic channel is defined by the surface of the die and a bottom surface of the fluidic channel is defined by the surface of the package substrate. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a surface; and an interposer having a fluidic channel between the surface of the die and the surface of the package substrate.

公开(公告)号：US20190385959A1

公开(公告)日：2019-12-19

申请号：US16012371

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Yikang Deng ,  Kyu Oh Lee ,  Ji Yong Park ,  Srinivas Pietambaram ,  Ying Wang ,  Chong Zhang ,  Rui Zhang ,  Junnan Zhao

IPC: H01L23/64 ,  H01L23/522 ,  H01L23/528 ,  H01L21/822 ,  H01L27/04 ,  H01F27/28 ,  H01F27/24

Abstract: Techniques are provided for an inductor at a second level interface between a first substrate and a second substrate. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first substrate, second conductive traces of a second non-semiconductor substrate, and a plurality of connectors configured to connect the first substrate with the second substrate. Each connector of the plurality of connecters can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.

公开(公告)号：US11721677B2

公开(公告)日：2023-08-08

申请号：US16234302

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Chong Zhang ,  Cheng Xu ,  Junnan Zhao ,  Ying Wang ,  Meizi Jiao

IPC: H01L21/00 ,  H01L25/16 ,  H01L23/538 ,  H01L49/02 ,  H01L23/498 ,  H01L21/56 ,  H01L23/528

CPC classification number: H01L25/16 ,  H01L21/568 ,  H01L23/49811 ,  H01L23/528 ,  H01L23/5386 ,  H01L28/40 ,  H01L2224/1623 ,  H01L2224/16265

Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.

公开(公告)号：US11696407B2

公开(公告)日：2023-07-04

申请号：US17560004

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Chong Zhang ,  Ying Wang ,  Junnan Zhao ,  Cheng Xu ,  Yikang Deng

IPC: H01L23/495 ,  H05K1/16 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H01F41/04 ,  H01F27/28 ,  H01F17/00 ,  H05K3/06 ,  H01L23/00

CPC classification number: H05K1/165 ,  H01F17/0013 ,  H01F27/2804 ,  H01F41/041 ,  H01F41/046 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H05K1/115 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/422 ,  H01F2017/002 ,  H01L23/49816 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/1427 ,  H01L2924/19042 ,  H01L2924/19102 ,  H05K3/06 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2203/072 ,  H05K2203/107

Abstract: Embodiments may include inductors with embedded magnetic cores and methods of making such inductors. In an embodiment, an integrated circuit package may include an integrated circuit die with a multi-phase voltage regulator electrically coupled to the integrated circuit die. In such embodiments, the multi-phase voltage regulator may include a substrate core and a plurality of inductors. The inductors may include a conductive through-hole disposed through the substrate core and a plugging layer comprising a dielectric material surrounding the conductive through-hole. In an embodiment, a magnetic sheath is formed around the plugging layer. In an embodiment, the magnetic sheath is separated from the plated through hole by the plugging layer. Additionally, a first layer comprising a dielectric material may be disposed over a first surface of the magnetic sheath, and a second layer comprising a dielectric material may be disposed over a second surface of the magnetic sheath.

公开(公告)号：US20230187205A1

公开(公告)日：2023-06-15

申请号：US18165422

申请日：2023-02-07

Applicant: Intel Corporation

Inventor： Ying Wang ,  Chong Zhang ,  Meizi Jiao ,  Junnan Zhao ,  Cheng Xu ,  Yikang Deng

IPC: H01L21/02 ,  H01L23/522 ,  H01L23/00 ,  H01L21/768 ,  H01L23/498

CPC classification number: H01L21/02422 ,  H01L23/5226 ,  H01L24/09 ,  H01L24/17 ,  H01L21/76816 ,  H01L23/49827 ,  H01L23/49894

Abstract: Embodiments may relate to a semiconductor package that includes a die and a glass core coupled with the die. The glass core may include a cavity with an interconnect structure therein. The interconnect structure may include pads on a first side that are coupled with the die, and pads on a second side opposite the first side. Other embodiments may be described and/or claimed.

公开(公告)号：US20220278038A1

公开(公告)日：2022-09-01

申请号：US17742816

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Ji Yong Park ,  Kyu Oh Lee ,  Yikang Deng ,  Zhichao Zhang ,  Liwei Cheng ,  Andrew James Brown ,  Cheng Xu ,  Jiwei Sun

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a core substrate with a first conductive structure having a first thickness on the core substrate, and a second conductive structure having a second thickness on the core substrate, where the first thickness is different than the second thickness.

公开(公告)号：US11335632B2

公开(公告)日：2022-05-17

申请号：US15857238

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Prithwish Chatterjee ,  Junnan Zhao ,  Sai Vadlamani ,  Ying Wang ,  Rahul Jain ,  Andrew J. Brown ,  Lauren A. Link ,  Cheng Xu ,  Sheng C. Li

IPC: H01L27/28 ,  H01L23/498 ,  H01L21/48 ,  H01F27/28 ,  H01F41/04 ,  H01L25/16 ,  H01L23/00

Abstract: Methods/structures of forming in-package inductor structures are described. Embodiments include a substrate including a dielectric material, the substrate having a first side and a second side. A conductive trace is located within the dielectric material. A first layer is on a first side of the conductive trace, wherein the first layer comprises an electroplated magnetic material, and wherein a sidewall of the first layer is adjacent the dielectric material. A second layer is on a second side of the conductive trace, wherein the second layer comprises the electroplated magnetic material, and wherein a sidewall of the second layer is adjacent the dielectric material.

公开(公告)号：US20210305154A1

公开(公告)日：2021-09-30

申请号：US16829336

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Ying Wang ,  Yikang Deng ,  Junnan Zhao ,  Andrew James Brown ,  Cheng Xu ,  Kaladhar Radhakrishnan

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L49/02

Abstract: Disclosed herein are magnetic structures in integrated circuit (IC) package supports, as well as related methods and devices. For example, in some embodiments, an IC package support may include a conductive line, a magnetic structure around the conductive line, and material stubs at side faces of the magnetic structure.

公开(公告)号：US10971492B2

公开(公告)日：2021-04-06

申请号：US16855376

申请日：2020-04-22

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Rahul Jain ,  Seo Young Kim ,  Kyu Oh Lee ,  Ji Yong Park ,  Sai Vadlamani ,  Junnan Zhao

IPC: H01L27/07 ,  H01L23/64 ,  H01L23/522 ,  H01L23/00 ,  H01L49/02

Abstract: Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.