公开(公告)号：US11380609B2

公开(公告)日：2022-07-05

申请号：US15985348

申请日：2018-05-21

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Jiwei Sun ,  Ji Yong Park ,  Kyu Oh Lee ,  Yikang Deng ,  Zhichao Zhang ,  Liwei Cheng ,  Andrew James Brown

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a core substrate with a first conductive structure having a first thickness on the core substrate, and a second conductive structure having a second thickness on the core substrate, where the first thickness is different than the second thickness.

公开(公告)号：US20200168536A1

公开(公告)日：2020-05-28

申请号：US16202690

申请日：2018-11-28

Applicant: Intel Corporation

Inventor： Lauren Ashley Link ,  Andrew James Brown ,  Prithwish Chatterjee ,  Sai Vadlamani ,  Ying Wang ,  Chong Zhang

IPC: H01L23/498 ,  H01L23/15 ,  H01L23/64

Abstract: Disclosed herein are asymmetric cored integrated circuit (IC) package supports, and related devices and methods. For example, in some embodiments, an IC package support may include a core region having a first face and an opposing second face, a first buildup region at the first face of the core region, and a second buildup region at the second face of the core region. A thickness of the first buildup region may be different than a thickness of the second buildup region. In some embodiments, an inductor may be included in the core region.

公开(公告)号：US11552008B2

公开(公告)日：2023-01-10

申请号：US16202690

申请日：2018-11-28

Applicant: Intel Corporation

Inventor： Lauren Ashley Link ,  Andrew James Brown ,  Prithwish Chatterjee ,  Sai Vadlamani ,  Ying Wang ,  Chong Zhang

IPC: H01L23/498 ,  H01L23/64 ,  H01L23/15

Abstract: Disclosed herein are asymmetric cored integrated circuit (IC) package supports, and related devices and methods. For example, in some embodiments, an IC package support may include a core region having a first face and an opposing second face, a first buildup region at the first face of the core region, and a second buildup region at the second face of the core region. A thickness of the first buildup region may be different than a thickness of the second buildup region. In some embodiments, an inductor may be included in the core region.

公开(公告)号：US12288744B2

公开(公告)日：2025-04-29

申请号：US17742816

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Ji Yong Park ,  Kyu Oh Lee ,  Yikang Deng ,  Zhichao Zhang ,  Liwei Cheng ,  Andrew James Brown ,  Cheng Xu ,  Jiwei Sun

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a core substrate with a first conductive structure having a first thickness on the core substrate, and a second conductive structure having a second thickness on the core substrate, where the first thickness is different than the second thickness.

公开(公告)号：US20230345621A1

公开(公告)日：2023-10-26

申请号：US18344944

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Andrew James Brown ,  Rahul Jain ,  Dilan Seneviratne ,  Praneeth Kumar Akkinepally ,  Frank Truong

IPC: H05K1/02 ,  H01L23/498 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K1/0228 ,  H01L23/49822 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/111 ,  H05K1/181

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a dielectric layer, in a substrate, the dielectric layer including an electroless catalyst, wherein the electroless catalyst includes one or more of palladium, gold, silver, ruthenium, cobalt, copper, nickel, titanium, aluminum, lead, silicon, and tantalum; a first conductive trace having a first thickness in the dielectric layer, wherein the first thickness is between 4 um and 143 um; and a second conductive trace having a second thickness in the dielectric layer, wherein the second thickness is between 2 um and 141 um, wherein the first thickness is greater than the second thickness, and wherein the first conductive trace and the second conductive trace have sloped sidewalls.

公开(公告)号：US20190355654A1

公开(公告)日：2019-11-21

申请号：US15985348

申请日：2018-05-21

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Jiwei Sun ,  Ji Yong Park ,  Kyu Oh Lee ,  Yikang Deng ,  Zhichao Zhang ,  Liwei Cheng ,  Andrew James Brown

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a core substrate with a first conductive structure having a first thickness on the core substrate, and a second conductive structure having a second thickness on the core substrate, where the first thickness is different than the second thickness.

公开(公告)号：US11830809B2

公开(公告)日：2023-11-28

申请号：US16829336

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Ying Wang ,  Yikang Deng ,  Junnan Zhao ,  Andrew James Brown ,  Cheng Xu ,  Kaladhar Radhakrishnan

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53228 ,  H01L28/10

Abstract: Disclosed herein are magnetic structures in integrated circuit (IC) package supports, as well as related methods and devices. For example, in some embodiments, an IC package support may include a conductive line, a magnetic structure around the conductive line, and material stubs at side faces of the magnetic structure.

公开(公告)号：US11737208B2

公开(公告)日：2023-08-22

申请号：US16268813

申请日：2019-02-06

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Andrew James Brown ,  Rahul Jain ,  Dilan Seneviratne ,  Praneeth Kumar Akkinepally ,  Frank Truong

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H01L23/498

CPC classification number: H05K1/0228 ,  H01L23/49822 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface, wherein the substrate layer includes a photo-imageable dielectric (PID) and an electroless catalyst; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the first thickness is greater than the second thickness.

公开(公告)号：US11075130B2

公开(公告)日：2021-07-27

申请号：US16481216

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Lisa Ying Ying Chen ,  Lauren Ashley Link ,  Robert Alan May ,  Amruthavalli Pallavi Alur ,  Kristof Kuwawi Darmawikarta ,  Siddharth K. Alur ,  Sri Ranga Sai Boyapati ,  Andrew James Brown ,  Lilia May

IPC: H01L21/48 ,  H01L23/15 ,  C04B35/622 ,  C04B35/64 ,  H01L23/498 ,  G03F7/16 ,  G03F7/20 ,  G03F7/32

Abstract: Semiconductor packages including package substrates having polymer-derived ceramic cores are described. In an example, a package substrate includes a core layer including a polymer-derived ceramic. The polymer-derived ceramic may include filler particles to control shrinkage and reduce warpage of the core layer during fabrication and use of the package substrate. The core layer may include counterbores or blind holes to embed a contact pad or an electrical interconnect in the core layer. A semiconductor die may be mounted on the package substrate and may be electrically connected to the contact pad or the electrical interconnect.

公开(公告)号：US11444042B2

公开(公告)日：2022-09-13

申请号：US16000372

申请日：2018-06-05

Applicant: Intel Corporation

Inventor： Andrew James Brown ,  Ying Wang ,  Chong Zhang ,  Lauren Ashley Link ,  Yikang Deng

IPC: H01L23/64 ,  H01F3/14 ,  H01F27/06 ,  H01F41/02

Abstract: Disclosed herein are magnetic structures in integrated circuit (IC) package supports, as well as related methods and devices. For example, in some embodiments, an IC package support may include a conductive line and a magnetic structure around a top surface of the conductive line and side surfaces of the conductive line. The magnetic structure may have a tapered shape that narrows toward the conductive line.