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    REAL TIME INSTRUCTION TRACE PROCESSORS, METHODS, AND SYSTEMS
    31.
    发明申请
    REAL TIME INSTRUCTION TRACE PROCESSORS, METHODS, AND SYSTEMS 审中-公开
    实时跟踪处理器，方法和系统

    公开(公告)号：US20160117171A1

    公开(公告)日：2016-04-28

    申请号：US14992658

    申请日：2016-01-11

    Applicant: INTEL CORPORATION

    Inventor： Tsvika Kurts ,  Ofer Levy ,  Itamar Kazachinsky ,  Gabi Malka ,  Zeev Sperber ,  Jason W. Brandt

    IPC: G06F9/30 ,  G06F13/40

    CPC classification number: G06F9/30145 ,  G06F11/00 ,  G06F11/3471 ,  G06F11/36 ,  G06F13/4068 ,  G06F2201/865

    Abstract: A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.

    Abstract translation: 一方面的方法包括为处理器的第一逻辑处理器生成实时指令跟踪（RTIT）分组。 RTIT分组指示由第一逻辑处理器执行的软件的流程。 RTIT分组被存储在对应于第一逻辑处理器的RTIT队列中。 RTIT数据包主要通过处理器的固件从RTIT队列传送到存储器。 还公开了其它方法，装置和系统。

    Apparatuses, methods, and systems for instructions to compartmentalize code
    39.
    发明授权
    Apparatuses, methods, and systems for instructions to compartmentalize code 有权

    公开(公告)号：US11556341B2

    公开(公告)日：2023-01-17

    申请号：US17341068

    申请日：2021-06-07

    Applicant: Intel Corporation

    Inventor： Ravi Sahita ,  Deepak Gupta ,  Vedvyas Shanbhogue ,  David Hansen ,  Jason W. Brandt ,  Joseph Nuzman ,  Mingwei Zhang

    IPC: G06F9/30 ,  G06F9/38 ,  G06F12/14

    Abstract: Systems, methods, and apparatuses relating to instructions to compartmentalize memory accesses and execution (e.g., non-speculative and speculative) are described. In one embodiment, a compartment manager circuit is to determine, when a compartment control register of a hardware processor core is set to an enable value, that a first subset of code requested for execution on the hardware processor core in user privilege is within a first compartment of memory, load a first compartment descriptor for the first compartment into one or more registers of the hardware processor core from the memory, check if the first compartment is marked in the first compartment descriptor, within the one or more registers of the hardware processor core, as a management compartment, and, when the first compartment is marked in the first compartment descriptor as the management compartment, allowing the first subset of the code within the first compartment to load a second compartment descriptor for a second compartment of the memory into the one or more registers of the hardware processor core from the memory, switching execution from the first subset of code within the first compartment to a second subset of code in user privilege within the second compartment, allowing speculative memory accesses for the second subset of code only within the second compartment, and preventing a memory access outside of the second compartment for the second subset of code as indicated by the second compartment descriptor stored within the one or more registers of the hardware processor core.

    System, Apparatus And Methods For Minimum Serialization In Response To Non-Serializing Register Write Instruction
    40.
    发明申请
    System, Apparatus And Methods For Minimum Serialization In Response To Non-Serializing Register Write Instruction 有权

    公开(公告)号：US20220413860A1

    公开(公告)日：2022-12-29

    申请号：US17358098

    申请日：2021-06-25

    Applicant: Intel Corporation

    Inventor： Kameswar Subramaniam ,  Jason W. Brandt

    IPC: G06F9/30 ,  G06F9/38

    Abstract: In one embodiment, a processor includes: a plurality of registers; a front end circuit to fetch and decode a non-serializing register write instruction, the non-serializing register write instruction to cause a value to be stored in a first register of the plurality of registers; and an execution circuit coupled to the front end circuit. The execution circuit, in response to the non-serializing register write instruction, is to determine an amount of serialization for the non-serializing register write instruction and execute the non-serializing register write instruction according to the amount of serialization. Other embodiments are described and claimed.

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