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    MICROELECTRONIC ASSEMBLIES
    31.
    发明申请
    MICROELECTRONIC ASSEMBLIES 有权

    公开(公告)号：US20220254754A1

    公开(公告)日：2022-08-11

    申请号：US17728813

    申请日：2022-04-25

    Applicant: Intel Corporation

    Inventor： Adel A. ELSHERBINI ,  Henning BRAUNISCH ,  Aleksandar ALEKSOV ,  Shawna M. LIFF ,  Johanna M. SWAN ,  Patrick MORROW ,  Kimin JUN ,  Brennen MUELLER ,  Paul B. FISCHER

    IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00

    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.

    STACKED PACKAGE WITH ELECTRICAL CONNECTIONS CREATED USING HIGH THROUGHPUT ADDITIVE MANUFACTURING
    36.
    发明申请
    STACKED PACKAGE WITH ELECTRICAL CONNECTIONS CREATED USING HIGH THROUGHPUT ADDITIVE MANUFACTURING 审中-公开

    公开(公告)号：US20200235082A1

    公开(公告)日：2020-07-23

    申请号：US16651331

    申请日：2017-09-30

    Applicant: Intel Corporation

    Inventor： Feras EID ,  Johanna M. SWAN ,  Shawna M. LIFF

    IPC: H01L25/10 ,  H01L25/00 ,  H01L23/367 ,  H01L21/48

    Abstract: A device package and a method of forming the device package are described. The device package includes one or more dies disposed on a first substrate. The device packages further includes one or more interconnects vertically disposed on the first substrate, and a mold layer disposed over and around the first die, the one or more interconnects, and the first substrate. The device package has a second die disposed on a second substrate, wherein the first substrate is electrically coupled to the second substrate with the one or more interconnects, and wherein the one or more interconnects are directly disposed on at least one of a top surface of the first substrate and a bottom surface of the second substrate without an adhesive layer. The device package may include one or more interconnects having one or more different thicknesses or heights at different locations on the first substrate.

    PACKAGE WITH A HIGHLY CONDUCTIVE LAYER DEPOSITED ON DIE USING THROUGHPUT ADDITIVE DEPOSITION PRIOR TO TIM1 DISPENSE
    37.
    发明申请
    PACKAGE WITH A HIGHLY CONDUCTIVE LAYER DEPOSITED ON DIE USING THROUGHPUT ADDITIVE DEPOSITION PRIOR TO TIM1 DISPENSE 审中-公开

    公开(公告)号：US20200227335A1

    公开(公告)日：2020-07-16

    申请号：US16639545

    申请日：2017-09-30

    Applicant: Intel Corporation

    Inventor： Feras EID ,  Johanna M. SWAN ,  Sergio CHAN ARGUEDAS ,  John J. BEATTY

    IPC: H01L23/367 ,  H01L21/48 ,  H01L49/02

    Abstract: A device package and a method of forming a device package are described. The device package has dies disposed on a substrate, and one or more layers with a high thermal conductivity, referred to as the highly-conductive (HC) intermediate layers, disposed on the dies on the substrate. The device package further includes a lid with legs on an outer periphery of the lid, a top surface, and a bottom surface. The legs of the lid are attached to the substrate with a sealant. The bottom surface of the lid is disposed over the one or more HC intermediate layers and the one or more dies on the substrate. The device package may also include thermal interface materials (TIMs) disposed on the HC intermediate layers. The TIMs may be disposed between the bottom surface of the lid and one or more top surfaces of the HC intermediate layers.

    ACTIVE VENTING GARMENT USING PIEZOELECTRIC ELEMENTS
    39.
    发明申请
    ACTIVE VENTING GARMENT USING PIEZOELECTRIC ELEMENTS 审中-公开

    公开(公告)号：US20190297975A1

    公开(公告)日：2019-10-03

    申请号：US16303386

    申请日：2016-07-02

    Applicant: Intel Corporation

    Inventor： Aleksandar ALEKSOV ,  Sasha N. OSTER ,  Feras EID ,  Shawna M. LIFF ,  Thomas L. SOUNART ,  Johanna M. SWAN ,  Baris BICEN ,  Valluri R. RAO

    IPC: A41D27/28 ,  A41D13/00 ,  A41D27/24 ,  A61M35/00 ,  A61M5/145

    Abstract: Embodiments of the invention include an active venting system. According to an embodiment of the invention, the active venting system may include a substrate having one or more seams formed through the substrate. In order to open the vents defined by the seams through the substrate, a piezoelectric layer may be formed proximate to one or more of the seams. Additional embodiments may include a first electrode and a second electrode that contact the piezoelectric layer in order to provide a voltage differential across the piezoelectric layer. In an embodiment the active venting system may be integrated into a garment. In such an embodiment, the garment may also include an electronics module for controlling the actuators. Additionally, conductive traces may be printed on the garment or sewn into the garment to provide electrical connections from the electronics module to each of the piezoelectric actuators.

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