公开(公告)号：US10514924B2

公开(公告)日：2019-12-24

申请号：US15721261

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Venkateswara Madduri ,  Elmoustapha Ould-Ahmed-Vall ,  Mark Charney ,  Robert Valentine ,  Jesus Corbal ,  Binwei Yang

IPC: G06F9/30

Abstract: An apparatus and method for performing dual concurrent multiplications of packed data elements. For example one embodiment of a processor comprises: a decoder to decode a first instruction to generate a decoded instruction; a first source register to store a first plurality of packed doubleword data elements; a second source register to store a second plurality of packed doubleword data elements; and execution circuitry to execute the decoded instruction, the execution circuitry comprising: multiplier circuitry to multiply a first doubleword data element from the first source register with a second doubleword data element from the second source register to generate a first quadword product and to concurrently multiply a third doubleword data element from the first source register with a fourth doubleword data element from the second source register to generate a second quadword product; and a destination register to store the first quadword product and the second quadword product as first and second packed quadword data elements.

公开(公告)号：US10481910B2

公开(公告)日：2019-11-19

申请号：US15721466

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Venkateswara Madduri ,  Elmoustapha Ould-Ahmed-Vall ,  Jesus Corbal ,  Mark Charney ,  Robert Valentine ,  Binwei Yang

IPC: G06F9/30

Abstract: An apparatus and method for performing right-shifting operations on packed quadword data. For example, one embodiment of a processor comprises: a decoder to decode a right-shift instruction to generate a decoded right-shift instruction; a first source register to store a plurality of packed quadwords data elements; execution circuitry to execute the decoded right-shift instruction, the execution circuitry comprising shift circuitry to right-shift at least first and second packed quadword data elements from first and second packed quadword data element locations, respectively, in the first source register by an amount specified in an immediate value or in a control value in a second source register, to generate first and second right-shifted quadwords; the execution circuitry to cause selection of 16 most significant bits of the first and second right-shifted quadwords to be written to 16 least significant bit regions of first and second quadword data element locations, respectively, of a destination register; and the destination register to store the specified set of the 16 most significant bits of the first and second right-shifted quadwords.

公开(公告)号：US20190196826A1

公开(公告)日：2019-06-27

申请号：US15850071

申请日：2017-12-21

Applicant: Intel Corporation

Inventor： Venkateswara Madduri ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Mark Charney ,  Jesus Corbal ,  Binwei Yang

IPC: G06F9/30 ,  G06F7/485

CPC classification number: G06F9/30145 ,  G06F7/485 ,  G06F9/30101

Abstract: An apparatus and method for performing addition of signed packed data values using rotation and halving. For example, one embodiment of a processor comprises: a decoder to decode an instruction to generate a decoded instruction, the instruction including an opcode, an immediate, and operands identifying a plurality of packed data source registers and a packed data destination register a first source register to store a first plurality of packed signed words; a second source register to store a second plurality of packed signed words; execution circuitry to execute the decoded instruction, the execution circuitry comprising: adder circuitry to add each packed signed word from the first source register with a selected packed signed word from the second source register to generate a plurality of signed word results, the adder circuitry to select each packed signed word from the second source register in accordance with a rotation value in the immediate of the instruction, the rotation value to indicate an amount of rotation to be applied to the packed signed words in the second source register prior to the adder circuitry performing the adding; and a destination register to store the plurality of signed word results in specified data element locations of the destination register.

公开(公告)号：US20190163473A1

公开(公告)日：2019-05-30

申请号：US15824333

申请日：2017-11-28

Applicant: Intel Corporation

Inventor： Robert Valentine ,  Mark Charney ,  Raanan Sade ,  Elmoustapha Ould-Ahmed-Vall ,  Jesus Corbal ,  Roman S. Dubtsov

IPC: G06F9/30

CPC classification number: G06F9/3001 ,  G06F7/4806 ,  G06F7/4812 ,  G06F9/3013 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/382 ,  G06F9/3824 ,  G06F17/10

Abstract: An embodiment of the invention is a processor including execution circuitry to calculate, in response to a decoded instruction, a result of a complex multiplication of a first complex number and a second complex number. The calculation includes a first operation to calculate a first term of a real component of the result and a first term of the imaginary component of the result. The calculation also includes a second operation to calculate a second term of the real component of the result and a second term of the imaginary component of the result. The processor also includes a decoder, a first source register, and a second source register. The decoder is to decode an instruction to generate the decoded instruction. The first source register is to provide the first complex number and the second source register is to provide the second complex number.

公开(公告)号：US20190102182A1

公开(公告)日：2019-04-04

申请号：US15721458

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Venkateswara Madduri ,  Elmoustapha Ould-Ahmed-Vall ,  Jesus Corbal ,  Mark Charney ,  Robert Valentine ,  Binwei Yang

IPC: G06F9/30

Abstract: An apparatus and method for performing dual concurrent multiplications of packed data elements. For example one embodiment of a processor comprises: a decoder to decode a first instruction to generate a decoded instruction; a first source register to store a first plurality of packed data elements; a second source register to store a second plurality of packed data elements; execution circuitry to execute the decoded instruction, the execution circuitry comprising: multiplier circuitry to perform concurrent dual multiplications of a first packed data element from the first source register with a second packed data element from the second source register and a third packed data element from the first source register with a fourth packed data element from the second source register to generate first and second products, respectively, wherein the first and third packed data elements have a width twice as large as a width of the second and fourth packed data elements; the multiplier circuitry to select the first and third packed data elements from the first source register and the second and fourth packed data elements from the second source register in accordance with the immediate to generate the first and second products.

公开(公告)号：US10223114B1

公开(公告)日：2019-03-05

申请号：US15721602

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Venkateswara Madduri ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Mark Charney

IPC: G06F9/30 ,  G06F7/483

Abstract: Embodiments of instructions and methods of execution of said instructions and resources to execute said instructions are detailed. For example, in an embodiment, a processor comprising: decode circuitry to decode an instruction having fields for an opcode, a packed data source operand identifier, and a packed data destination operand identifier; and execution circuitry to execute the decoded instruction to convert a data element from a least significant packed data element position of the identified packed data source operand from a fixed-point representation to a floating point representation, store the floating point representation into a 32-bit least significant packed data element position of the identified packed data destination operand, and zero all remaining packed data elements of the identified packed data destination operand is described.

公开(公告)号：US20250117218A1

公开(公告)日：2025-04-10

申请号：US18927097

申请日：2024-10-25

Applicant: Intel Corporation

Inventor： Alexander Heinecke ,  Naveen Mellempudi ,  Robert Valentine ,  Mark Charney ,  Christopher Hughes ,  Evangelos Georganas ,  Zeev Sperber ,  Amit Gradstein ,  Simon Rubanovich

IPC: G06F9/30 ,  G06F9/38

Abstract: Techniques for converting FP16 to BF8 using bias are described. An exemplary embodiment utilizes decoder circuitry to decode a single instruction, the single instruction to include one or more fields to identify a first source operand, one or more fields to identify a second source operand, one or more fields to identify a source/destination operand, and one or more fields for an opcode, wherein the opcode is to indicate that execution circuitry is to convert packed half-precision data from the identified first and second sources to packed bfloat8 data using bias terms from the identified source/destination operand and store the packed bfloat8 data into corresponding data element positions of the identified source/destination operand; and execution circuitry to execute the decoded instruction according to the opcode to convert packed half-precision data from the identified first and second sources to packed bfloat8 data using bias terms from the identified source/destination operand and store the packed bfloat8 data into corresponding data element positions of the identified source/destination operand.

公开(公告)号：US20240248720A1

公开(公告)日：2024-07-25

申请号：US18627907

申请日：2024-04-05

Applicant: Intel Corporation

Inventor： Alexander Heinecke ,  Naveen Mellempudi ,  Robert Valentine ,  Mark Charney ,  Christopher Hughes ,  Evangelos Georganas ,  Zeev Sperber ,  Amit Gradstein ,  Simon Rubanovich

IPC: G06F9/30 ,  G06F7/499 ,  H03M7/24

CPC classification number: G06F9/30145 ,  G06F7/49947 ,  G06F9/30025 ,  G06F9/30036 ,  H03M7/24

Abstract: Techniques for converting FP16 data elements to BF8 data elements using a single instruction are described. An exemplary apparatus includes decoder circuitry to decode a single instruction, the single instruction to include a one or more fields to identify a source operand, one or more fields to identify a destination operand, and one or more fields for an opcode, the opcode to indicate that execution circuitry is to convert packed half-precision floating-point data from the identified source to packed bfloat8 data and store the packed bfloat8 data into corresponding data element positions of the identified destination operand; and execution circuitry to execute the decoded instruction according to the opcode to convert packed half-precision floating-point data from the identified source to packed bfloat8 data and store the packed bfloat8 data into corresponding data element positions.

公开(公告)号：US11960884B2

公开(公告)日：2024-04-16

申请号：US17517351

申请日：2021-11-02

Applicant: Intel Corporation

Inventor： Robert Valentine ,  Mark Charney ,  Raanan Sade ,  Elmoustapha Ould-Ahmed-Vall ,  Jesus Corbal ,  Roman S. Dubtsov

IPC: G06F9/30 ,  G06F7/48 ,  G06F9/38 ,  G06F17/10

CPC classification number: G06F9/3001 ,  G06F7/4812 ,  G06F9/30014 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/3016 ,  G06F7/4806 ,  G06F9/30167 ,  G06F9/382 ,  G06F9/3824 ,  G06F17/10

Abstract: An embodiment of the invention is a processor including execution circuitry to calculate, in response to a decoded instruction, a result of a complex multiplication of a first complex number and a second complex number. The calculation includes a first operation to calculate a first term of a real component of the result and a first term of the imaginary component of the result. The calculation also includes a second operation to calculate a second term of the real component of the result and a second term of the imaginary component of the result. The processor also includes a decoder, a first source register, and a second source register. The decoder is to decode an instruction to generate the decoded instruction. The first source register is to provide the first complex number and the second source register is to provide the second complex number.

公开(公告)号：US11645080B2

公开(公告)日：2023-05-09

申请号：US17903307

申请日：2022-09-06

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Mark Charney ,  Michael Mishaeli ,  Robert Valentine ,  Itai Ravid ,  Jason W. Brandt ,  Gilbert Neiger ,  Baruch Chaikin ,  Efraim Rotem

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3851 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/3836

Abstract: Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.