公开(公告)号：US10558254B2

公开(公告)日：2020-02-11

申请号：US15477042

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Eric J. Hoekstra ,  Kiran C. Veernapu ,  Prasoonkumar Surti ,  Vasanth Ranganathan ,  Kamal Sinha ,  Balaji Vembu ,  Eric J. Asperheim ,  Sanjeev S. Jahagirdar ,  Joydeep Ray

IPC: G06F3/06 ,  G06F1/3225 ,  G06F1/3234

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive data for a current write operation to a memory, determine a number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory and in response to a determination that the number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory exceeds a threshold, to toggle a plurality of bits in the data for the current write operation to create an encoded data set and set an indicator bit to a value which indicates that the plurality of bits have been toggled. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200042417A1

公开(公告)日：2020-02-06

申请号：US16526069

申请日：2019-07-30

Applicant: Intel Corporation

Inventor： Nikos Kaburlasos ,  Balaji Vembu ,  Josh B. Mastronarde ,  Altug Koker ,  Eric C. Samson ,  Abhishek R. Appu ,  Kiran C. Veernapu ,  Joydeep Ray ,  Vasanth Ranganathan ,  Sanjeev S. Jahagirdar

IPC: G06F11/30 ,  G06F1/324 ,  G06F1/3206 ,  G06F1/3296 ,  G05F1/10 ,  G05F1/571 ,  G06F11/32 ,  G06F11/34

Abstract: Methods and apparatus relating to techniques for power management. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to generate a voltage/frequency curve for at least one of a core or a sub-core in a processor and manage an operating voltage level of the at least one of a core or a sub-core using the voltage/frequency curve. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200019221A1

公开(公告)日：2020-01-16

申请号：US16578641

申请日：2019-09-23

Applicant: Intel Corporation

Inventor： Sanjeev S. Jahagirdar ,  Satish K. Damaraju ,  Yun-Han Chen ,  Ryan D. Wells ,  Inder M. Sodhi ,  Vishram Sarurkar ,  Ken Drottar ,  Ashish V. Choubal ,  Rabiul Islam

IPC: G06F1/26 ,  G06F1/3296 ,  G06F1/3234 ,  G06F9/50

Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.

公开(公告)号：US10394564B2

公开(公告)日：2019-08-27

申请号：US15640216

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Inder M. Sodhi ,  Sanjeev S. Jahagirdar

IPC: G06F1/32 ,  G06F9/30 ,  G06F1/08 ,  G06F9/38

Abstract: According to one embodiment, a processor includes an instruction decoder to decode instruction and a execution unit to execute instructions, the execution unit being associated with a capture logic to periodically capture operating heuristics of the execution unit, a detection logic coupled to the execution unit to evaluate the captured operating heuristics to determine whether there is a need to adjust an operating point of the execution unit, and a control logic coupled to the detection logic and the execution unit to adjust the operating point of the execution unit based on the evaluation of the operating heuristics.

公开(公告)号：US10049080B2

公开(公告)日：2018-08-14

申请号：US15431527

申请日：2017-02-13

Applicant: Intel Corporation

Inventor： Varghese George ,  Sanjeev S. Jahagirdar ,  Deborah T. Marr

IPC: G06F15/80 ,  G06F13/40 ,  G06F1/32

Abstract: A method is described that entails operating enabled cores of a multi-core processor such that both cores support respective software routines with a same instruction set, a first core being higher performance and consuming more power than a second core under a same set of applied supply voltage and operating frequency.

公开(公告)号：US09753531B2

公开(公告)日：2017-09-05

申请号：US14603955

申请日：2015-01-23

Applicant: Intel Corporation

Inventor： Sanjeev S. Jahagirdar ,  Ryan Wells ,  Inder Sodhi

IPC: G06F1/32 ,  G06F13/24

CPC classification number: G06F1/3293 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3296 ,  G06F13/24 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

Abstract: A processor may determine the actual residency time of a non-core domain residing in a power saving state and based on the actual residency time the processor may determine an optimal power saving state (P-state) for the processor. In response to the non-core domain entering a power saving state, an interrupt generator (IG) may generate a first interrupt and the device drivers or an operating system may use the first interrupt to start a timer (first value). In response to the non-core domain exiting the power saving state, the IG may generate a second interrupt and the device drivers or an operating system may use the second interrupt to stop the timer (final value). The power management unit may use the final and the first value to determine the actual residency time.

公开(公告)号：US20170139454A1

公开(公告)日：2017-05-18

申请号：US15416400

申请日：2017-01-26

Applicant: Intel Corporation

Inventor： Sandeep K. Venishetti ,  Sanjeev S. Jahagirdar ,  Srinivas Thota

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/189 ,  G06F1/263 ,  G06F1/3287 ,  H02J2003/001 ,  Y02D10/171 ,  Y10T307/352

Abstract: An apparatus includes a distribution network that includes circuitry configured to receive first power from a first voltage source and second power from a second voltage source, and to deliver power to each of a plurality of electronic circuitry blocks (ECBs), including to deliver first ECB power to a first ECB and second ECB power to a second ECB. The first ECB power includes a first portion of the first power and a first portion of the second power. The apparatus also includes power management logic to dynamically adjust the power to be provided to each ECB. Responsive to a change in a first activity level of the first ECB, the power management logic is to change the first ECB power by adjustment of the first portion of the first power and adjustment of the first portion of the second power. Other embodiments are described and claimed.

公开(公告)号：US12061831B2

公开(公告)日：2024-08-13

申请号：US18474361

申请日：2023-09-26

Applicant: Intel Corporation

Inventor： Eric J. Asperheim ,  Subramaniam Maiyuran ,  Kiran C. Veernapu ,  Sanjeev S. Jahagirdar ,  Balaji Vembu ,  Devan Burke ,  Philip R. Laws ,  Kamal Sinha ,  Abhishek R. Appu ,  Elmoustapha Ould-Ahmed-Vall ,  Peter L. Doyle ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Altug Koker

IPC: G09G5/391 ,  G06F3/01 ,  G06F3/0484 ,  G06F3/14 ,  G09G5/00

CPC classification number: G06F3/1438 ,  G06F3/013 ,  G06F3/0484 ,  G09G5/391 ,  G09G5/001 ,  G09G2340/0435 ,  G09G2352/00 ,  G09G2354/00 ,  G09G2360/08 ,  G09G2360/121

Abstract: In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.

公开(公告)号：US11816384B2

公开(公告)日：2023-11-14

申请号：US17959374

申请日：2022-10-04

Applicant: Intel Corporation

Inventor： Eric J. Asperheim ,  Subramaniam Maiyuran ,  Kiran C. Veernapu ,  Sanjeev S. Jahagirdar ,  Balaji Vembu ,  Devan Burke ,  Philip R. Laws ,  Kamal Sinha ,  Abhishek R. Appu ,  Elmoustapha Ould-Ahmed-Vall ,  Peter L. Doyle ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Altug Koker

IPC: G06F3/14 ,  G06F3/01 ,  G09G5/391 ,  G06F3/0484 ,  G09G5/00

CPC classification number: G06F3/1438 ,  G06F3/013 ,  G06F3/0484 ,  G09G5/391 ,  G09G5/001 ,  G09G2340/0435 ,  G09G2352/00 ,  G09G2354/00 ,  G09G2360/08 ,  G09G2360/121

Abstract: In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.

公开(公告)号：US20220206853A1

公开(公告)日：2022-06-30

申请号：US17520583

申请日：2021-11-05

Applicant: Intel Corporation

Inventor： Abhishek R Appu ,  Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Kamal Sinha ,  Prasoonkumar Surti ,  Kiran C. Veernapu ,  Subramaniam Maiyuran ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Guei-Yuan Lueh ,  David Puffer ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Josh B. Mastronarde ,  Linda L. Hurd ,  Travis T. Schluessler ,  Tomasz Janczak ,  Abhishek Venkatesh ,  Kai Xiao ,  Slawomir Grajewski

IPC: G06F9/50 ,  G06F1/329 ,  G06F9/48 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.