公开(公告)号：US11853212B2

公开(公告)日：2023-12-26

申请号：US17713267

申请日：2022-04-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tu-An T. Nguyen ,  Matthias Klein ,  Gregory William Alexander ,  Jason D. Kohl ,  Vesselina Papazova

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: Embodiments are for preemptive tracking of remote requests for decentralized hot cache line fairness tracking. Authority is requested for a cache line in conjunction with querying for outstanding requests for the cache line. One or more responses are received regarding the outstanding requests for the cache line. In response to receiving the one or more responses regarding the outstanding requests and in advance of receiving the authority for the cache line, the outstanding requests are preemptively tracked in a requested structure associated with the cache line.

公开(公告)号：US20230315638A1

公开(公告)日：2023-10-05

申请号：US17713264

申请日：2022-04-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tu-An T. Nguyen ,  Matthias Klein ,  Gregory William Alexander ,  Jason D. Kohl ,  Winston Herring ,  Timothy Bronson ,  CHRISTIAN JACOBI

IPC: G06F12/084 ,  G06F12/0815 ,  G06F12/0897 ,  G06F9/38 ,  G06F9/34

CPC classification number: G06F12/084 ,  G06F12/0815 ,  G06F9/34 ,  G06F9/3816 ,  G06F12/0897

Abstract: Embodiments are for using a decentralized hot cache line tracking fairness mechanism. In response to receiving an incoming request to access a cache line, a determination is made to grant access to the cache line based on a requested state and a serviced state used for maintaining the cache line, a structure comprising the requested and serviced states. In response to the determination to grant access to the cache line, the requested state and the serviced state are transferred along with data of the cache line.

公开(公告)号：US11461151B2

公开(公告)日：2022-10-04

申请号：US17237167

申请日：2021-04-22

Applicant: International Business Machines Corporation

Inventor： Robert J. Sonnelitter, III ,  Michael Fee ,  Craig R. Walters ,  Arthur O'Neill ,  Matthias Klein

IPC: G06F9/52 ,  G06F9/48 ,  G06F12/0802 ,  G06F9/54 ,  G06F9/38

Abstract: Embodiments of the present invention are directed to a computer-implemented method for controller address contention assumption. A non-limiting example computer-implemented method includes a shared controller receiving a fetch request for data from a first requesting agent, the receiving via at least one intermediary controller. The shared controller performs an address compare using a memory address of the data. In response to the memory address matching a memory address stored in the shared controller, the shared controller acknowledges the at least one intermediary controller's fetch request, wherein upon acknowledgement, the at least one intermediary controller resets, wherein the acknowledging comprises exchanging tokens by the shared controller and the at least one intermediary controller, wherein the at least one intermediary controller transmits an identity of the first requesting agent and a type of operation associated with the requested data, and wherein the shared controller transmits an acceptance.

公开(公告)号：US11223369B2

公开(公告)日：2022-01-11

申请号：US16373375

申请日：2019-04-02

Applicant: International Business Machines Corporation

Inventor： Bulent Abali ,  Ashutosh Misra ,  Girish G. Kurup ,  Deepankar Bhattacharjee ,  Matthias Klein

IPC: H03M7/40 ,  H03M7/42 ,  G06F16/22 ,  H03M7/30

Abstract: Compressing data includes hashing a first token length of an incoming data steam into a hash table, where the first token length includes a plurality of bytes. A second token length of the incoming data stream may be hashed into the hash table. The second token may be larger than the first token length and includes the plurality of bytes. The method may further include automatically comparing which token length enabled more efficient data compression, and automatically adjusting at least one of the first and second token lengths based on the comparison.

公开(公告)号：US20220004387A1

公开(公告)日：2022-01-06

申请号：US17480337

申请日：2021-09-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Christoph Raisch ,  Marco Kraemer ,  Frank Siegfried Lehnert ,  Matthias Klein ,  Jonathan D. Bradbury ,  Christian Jacobi ,  Brenton Belmar ,  Peter Dana Driever

IPC: G06F9/30 ,  G06F9/451 ,  G06F9/38 ,  G06F9/4401 ,  G06F9/54 ,  G06F11/07

Abstract: An input/output store instruction is handled. A data processing system includes a system nest communicatively coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is communicatively coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to an external device which is communicatively coupled to the input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed.

公开(公告)号：US20210240548A1

公开(公告)日：2021-08-05

申请号：US17237167

申请日：2021-04-22

Applicant: International Business Machines Corporation

Inventor： Robert J. Sonnelitter, III ,  Michael Fee ,  Craig R. Walters ,  Arthur O'Neill ,  Matthias Klein

IPC: G06F9/52 ,  G06F9/48 ,  G06F12/0802 ,  G06F9/54 ,  G06F9/38

Abstract: Embodiments of the present invention are directed to a computer-implemented method for controller address contention assumption. A non-limiting example computer-implemented method includes a shared controller receiving a fetch request for data from a first requesting agent, the receiving via at least one intermediary controller. The shared controller performs an address compare using a memory address of the data. In response to the memory address matching a memory address stored in the shared controller, the shared controller acknowledges the at least one intermediary controller's fetch request, wherein upon acknowledgement, the at least one intermediary controller resets, wherein the acknowledging comprises exchanging tokens by the shared controller and the at least one intermediary controller, wherein the at least one intermediary controller transmits an identity of the first requesting agent and a type of operation associated with the requested data, and wherein the shared controller transmits an acceptance.

公开(公告)号：US11074203B2

公开(公告)日：2021-07-27

申请号：US16775679

申请日：2020-01-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Christoph Raisch ,  Marco Kraemer ,  Frank Siegfried Lehnert ,  Matthias Klein ,  Jonathan D. Bradbury ,  Christian Jacobi ,  Peter Dana Driever ,  Brenton Belmar

IPC: G06F13/16 ,  G06F9/30

Abstract: An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers.

公开(公告)号：US11068266B2

公开(公告)日：2021-07-20

申请号：US16775784

申请日：2020-01-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Christoph Raisch ,  Marco Kraemer ,  Frank Siegfried Lehnert ,  Matthias Klein ,  Jonathan D. Bradbury ,  Christian Jacobi ,  Brenton Belmar ,  Peter Dana Driever

IPC: G06F9/30 ,  G06F9/54 ,  G06F11/30 ,  G06F11/07 ,  G06F11/14

Abstract: An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers. The system firmware includes a retry buffer and the core includes an analysis and retry logic.

公开(公告)号：US11061685B2

公开(公告)日：2021-07-13

申请号：US16286985

申请日：2019-02-27

Applicant: International Business Machines Corporation

Inventor： Louis P. Gomes ,  Bruce Giamei ,  Timothy Slegel ,  Mark Farrell ,  Matthias Klein

IPC: G06F3/00 ,  G06F9/38 ,  G06F9/46 ,  G06F9/30

Abstract: A method is provided that is executable by a processor of a computer. Note that the processor is communicatively coupled to a memory of the computer, and the memory stores a response block of a call command. In implementing the method, the processor defines a sub-functions field in the response block of the call command. Further the processor indicates that a set of functions of a set of instructions are installed and available at an interface based on a corresponding sub-functions flag within the sub-functions field being set. Note that the interface is also being executed on the computer and that the set of functions being represented by the corresponding sub-functions flag. The processor further indicates that the set of functions of the set of instructions are not installed based on the corresponding sub-functions flag not being set.

公开(公告)号：US20200250112A1

公开(公告)日：2020-08-06

申请号：US16775716

申请日：2020-01-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Christoph Raisch ,  Marco Kraemer ,  Frank Siegfried Lehnert ,  Matthias Klein ,  Jonathan D. Bradbury ,  Christian Jacobi ,  Brenton Belmar ,  Peter Dana Driever

IPC: G06F13/16 ,  G06F13/42

Abstract: An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers.