公开(公告)号：US20150179413A1

公开(公告)日：2015-06-25

申请号：US14636238

申请日：2015-03-03

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt

IPC: H01J37/32 ,  C23C16/513

CPC classification number: H01J37/32642 ,  C23C16/513 ,  H01J37/32009 ,  H01J37/32532 ,  H01J37/32651 ,  H01J37/32715 ,  H01J2237/3322 ,  H01J2237/3343 ,  H01L21/3065

Abstract: In accordance with an embodiment of the present invention, a process tool includes a chuck configured to hold a substrate. The chuck is disposed in a chamber. The process tool further includes a shielding unit with a central opening. The shielding unit is disposed in the chamber over the chuck.

Abstract translation: 根据本发明的实施例，处理工具包括配置成保持基板的卡盘。 卡盘设置在腔室中。 处理工具还包括具有中心开口的屏蔽单元。 屏蔽单元设置在卡盘上的腔室中。

公开(公告)号：US20150137144A1

公开(公告)日：2015-05-21

申请号：US14086886

申请日：2013-11-21

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt ,  Johannes Baumgartl ,  Manfred Kotek ,  Hans-Joachim Schulze

IPC: H01L21/8234 ,  H01L29/20 ,  H01L21/306 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L21/8234 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/32 ,  H01L21/6835 ,  H01L21/78 ,  H01L29/6659 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368

Abstract: In one embodiment, the semiconductor die includes a selective epitaxial layer including device regions, and a masking structure disposed around sidewalls of the epitaxial layer. The masking structure is part of an exposed surface of the semiconductor die.

Abstract translation: 在一个实施例中，半导体管芯包括包括器件区域的选择性外延层和设置在外延层的侧壁周围的掩模结构。 掩模结构是半导体管芯的暴露表面的一部分。

公开(公告)号：US09006109B2

公开(公告)日：2015-04-14

申请号：US13851691

申请日：2013-03-27

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt ,  Martin Zgaga

IPC: H01L21/311 ,  B81C1/00 ,  B81B3/00

CPC classification number: B81B3/001 ,  B81B3/0051 ,  B81C1/00531 ,  B81C1/00626 ,  B81C2201/0112 ,  B81C2201/0132 ,  H01L21/30655

Abstract: A method includes a step of performing a time multiplexed etching process, wherein the last etching step of the time multiplexed etching process is of a first time duration. After performing the time multiplexed etching process, an etching step having a second time duration is performed, wherein the second time duration is greater than the first time duration.

Abstract translation: 一种方法包括执行时间复用蚀刻工艺的步骤，其中时间复用蚀刻工艺的最后一个蚀刻步骤是第一持续时间。 在执行时间复用蚀刻处理之后，执行具有第二持续时间的蚀刻步骤，其中第二持续时间大于第一持续时间。

公开(公告)号：US20150064879A1

公开(公告)日：2015-03-05

申请号：US14013822

申请日：2013-08-29

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt ,  Gudrun Stranzl ,  Markus Zundel ,  Hubert Maier

IPC: H01L21/78 ,  B28D5/00 ,  H01J37/32

CPC classification number: H01J37/32009 ,  B28D5/00 ,  H01J2237/334 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834

Abstract: Various methods and apparatuses are provided relating to separation of a substrate into a plurality of parts. For example, first a partial separation is performed and then the partially separated substrate is completely separated into a plurality of parts.

Abstract translation: 提供了关于将基板分离成多个部件的各种方法和装置。 例如，首先进行部分分离，然后将部分分离的基板完全分离成多个部分。

公开(公告)号：US20150044856A1

公开(公告)日：2015-02-12

申请号：US14525233

申请日：2014-10-28

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt ,  Petra Fischer

IPC: H01L21/78 ,  H01L21/322

CPC classification number: H01L21/78 ,  H01L21/3043 ,  H01L21/306 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/322 ,  H01L21/6835 ,  H01L21/6836 ,  H01L29/1608 ,  H01L2221/68327

Abstract: A method for separating semiconductor die includes forming a porous region on a semiconductor wafer and separating the die at the porous region using mechanical or other means.

Abstract translation: 一种用于分离半导体管芯的方法包括在半导体晶片上形成多孔区域，并使用机械或其他方式在多孔区域分离管芯。

公开(公告)号：US10236204B2

公开(公告)日：2019-03-19

申请号：US15184804

申请日：2016-06-16

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt

IPC: H01L21/687 ,  H01L21/67 ,  H01L21/683 ,  C23C16/44 ,  C23C16/458 ,  C23C16/509 ,  C23C14/34 ,  C23C16/50 ,  H01L21/02 ,  H01L21/3065

Abstract: The semiconductor processing system includes a reactor chamber that has an upper wall and a lower wall. A hold member is disposed in the reactor chamber to hold a semiconductor substrate in such a way that it faces the lower wall of the reactor chamber.

公开(公告)号：US20180315713A1

公开(公告)日：2018-11-01

申请号：US16029934

申请日：2018-07-09

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Gudrun Stranzl ,  Manfred Engelhardt ,  Martin Zgaga

IPC: H01L23/544 ,  H01L21/78 ,  H01L21/3065

Abstract: An integrated circuit substrate and a method for manufacturing the same are disclosed. In an embodiment a method includes providing a wafer having a plurality of active areas, each active area being provided in a separate die area and for each active area, providing a code pattern outside the active area, the code pattern being associated with the die area.

公开(公告)号：US10043683B2

公开(公告)日：2018-08-07

申请号：US15358962

申请日：2016-11-22

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt

IPC: C23C16/00 ,  H01L21/67 ,  H01L21/683 ,  H01J37/32

Abstract: A chuck, a system including a chuck and a method for making a semiconductor device are disclosed. In one embodiment the chuck includes a first conductive region configured to be capacitively coupled to a first RF power generator, a second conductive region configured to be capacitively coupled to a second RF power generator and an insulation region that electrically insulates the first conductive region from the second conductive region.

公开(公告)号：US10020264B2

公开(公告)日：2018-07-10

申请号：US14698639

申请日：2015-04-28

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Gudrun Stranzl ,  Manfred Engelhardt ,  Martin Zgaga

IPC: H01L23/544 ,  H01L21/67 ,  H01L21/78 ,  H01L21/3065 ,  G06K7/14

CPC classification number: H01L23/544 ,  H01L21/30655 ,  H01L21/78 ,  H01L2223/54413 ,  H01L2223/54433 ,  H01L2223/5446 ,  H01L2223/54473

Abstract: The description discloses a method for use in manufacturing integrated circuit chips. The method comprises providing a wafer having a plurality of integrated circuits each provided in an separate active areas, and, for each active area, outside the active area, providing a code pattern that is associated with the integrated circuit. A computer-readable medium is also disclosed. Further, a manufacturing apparatus configured to receive a wafer and to remove material from the wafer so as to provide a scribe line to the wafer formed as a trench for use in separation of the wafer into dies is also disclosed. The description also discloses a wafer, an integrated circuit chip die substrate originating from a wafer of origin and carrying an integrated circuit, and an integrated circuit chip.

公开(公告)号：US09875926B2

公开(公告)日：2018-01-23

申请号：US14953362

申请日：2015-11-29

Applicant: Infineon Technologies AG

Inventor： Iris Moder ,  Ingo Muri ,  Johannes Baumgartl ,  Oliver Hellmund ,  Manfred Engelhardt ,  Hans-Joachim Schulze

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/20 ,  H01L21/02

CPC classification number: H01L21/76267 ,  H01L21/02238 ,  H01L21/02258 ,  H01L21/02647 ,  H01L21/2022 ,  H01L21/31144 ,  H01L21/7621 ,  H01L21/7624 ,  H01L21/76248 ,  H01L21/76264 ,  H01L21/76272 ,  H01L21/76281 ,  H01L21/76283 ,  H01L21/76286 ,  H01L21/76289 ,  H01L21/76297

Abstract: A method for fabricating a semiconductor device includes forming an opening in a first epitaxial lateral overgrowth region to expose a surface of the semiconductor substrate within the opening. The method further includes forming an insulation region at the exposed surface of the semiconductor substrate within the opening and filling the opening with a second semiconductor material to form a second epitaxial lateral overgrowth region using a lateral epitaxial growth process.