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    METHOD TO BUILD FAST TRANSMIT-RECEIVE SWITCHING ARCHITECTURE
    33.
    发明申请
    METHOD TO BUILD FAST TRANSMIT-RECEIVE SWITCHING ARCHITECTURE 审中-公开

    公开(公告)号：US20190089402A1

    公开(公告)日：2019-03-21

    申请号：US16131259

    申请日：2018-09-14

    Applicant: Integrated Device Technology, Inc.

    Inventor： Samet Zihir ,  Tumay Kanar

    IPC: H04B1/44 ,  H01Q3/36 ,  H01Q21/22 ,  H04B1/401

    Abstract: An apparatus includes a phased array antenna panel and one or more beam former circuits. The phased array antenna panel generally comprises a plurality of antenna elements. The plurality of antenna elements are generally arranged in one or more groups. The one or more beam former circuits may be mounted on the phased array antenna panel. Each beam former circuit is generally coupled to a respective group of the antenna elements. Each beam former circuit generally comprises a plurality of transceiver channels comprising a transmit channel and a receive channel. The phased array antenna panel is generally configured to distribute a control signal to each of the beam former circuits. Each of the transceiver channels is generally configured to switch between a transmit mode and a receive mode in response to the control signal.

    FAST MEMORY ACCESS CONTROL FOR PHASE AND GAIN
    34.
    发明申请
    FAST MEMORY ACCESS CONTROL FOR PHASE AND GAIN 审中-公开

    公开(公告)号：US20190089399A1

    公开(公告)日：2019-03-21

    申请号：US16100408

    申请日：2018-08-10

    Applicant: Integrated Device Technology, Inc.

    Inventor： Samet Zihir ,  Tumay Kanar ,  Naveen Krishna Yanduru

    IPC: H04B1/44 ,  H03F3/24 ,  H03G3/30 ,  H04B7/06 ,  H03F3/19 ,  H03F1/56 ,  H03K21/10

    Abstract: An apparatus includes a switching circuit and a plurality of registers. The switching circuit may be configured to generate a sequence of pulses in a plurality of control signals in response to a plurality of cycles of an enable signal. The registers may be hardwired as a plurality of subsets. Each of the subsets of the registers may be configured to (a) buffer a plurality of setting values received from a memory and (b) present the setting values from the registers to a plurality of transceiver circuits while a corresponding one of the control signals is in an active state.The transceiver circuits may be updated with the setting values from the registers within a predetermined time.

    METHOD FOR SEPARATELY BIASING POWER AMPLIFIER FOR ADDITIONAL POWER CONTROL
    36.
    发明申请
    METHOD FOR SEPARATELY BIASING POWER AMPLIFIER FOR ADDITIONAL POWER CONTROL 审中-公开

    公开(公告)号：US20190089070A1

    公开(公告)日：2019-03-21

    申请号：US16132877

    申请日：2018-09-17

    Applicant: Integrated Device Technology, Inc.

    Inventor： Samet Zihir ,  Tumay Kanar

    IPC: H01Q21/22 ,  H01Q3/28 ,  H01Q21/24

    Abstract: An apparatus includes a phased array antenna panel and one or more beam former circuits mounted on the phased array antenna panel. The phased array antenna panel generally comprises a plurality of antenna elements. The plurality of antenna elements are generally arranged in one or more groups. Each beam former circuit may be coupled to a respective group of the antenna elements. Each beam former circuit generally comprises a plurality of transceiver channels. Each transceiver channel generally comprises a power amplifier circuit configured, when operating in a transmit mode, to drive a respective one of the antenna elements. The power amplifier circuit generally comprises separate bias and voltage supply inputs providing additional power control.

    HARD-WIRED ADDRESS FOR PHASED ARRAY ANTENNA PANELS
    37.
    发明申请
    HARD-WIRED ADDRESS FOR PHASED ARRAY ANTENNA PANELS 审中-公开

    公开(公告)号：US20190089067A1

    公开(公告)日：2019-03-21

    申请号：US16121891

    申请日：2018-09-05

    Applicant: Integrated Device Technology, Inc.

    Inventor： Samet Zihir ,  Tumay Kanar ,  Naveen Krishna Yanduru

    IPC: H01Q21/20 ,  H01Q21/00 ,  H01Q21/06 ,  H01Q1/26 ,  H01Q3/46

    Abstract: An apparatus includes a phased array antenna panel and a plurality of beam former circuits. The phased array antenna panel generally comprises a plurality of antenna elements. The plurality of beam former circuits are each mounted on the phased array antenna panel adjacent to a number of the antenna elements. Each beam former circuit has one or more ports directly coupled to each of the adjacent antenna elements. Each beam former circuit may be configured to generate a plurality of radio-frequency output signals at the ports while in a transmit mode and receive a plurality of radio-frequency input signals at the ports while in a receive mode. Each beam former circuit generally implements a hard-wired address.

    RADIO-FREQUENCY SIGNAL SHIELDING AND CHANNEL ISOLATION
    38.
    发明申请
    RADIO-FREQUENCY SIGNAL SHIELDING AND CHANNEL ISOLATION 审中-公开

    公开(公告)号：US20190089048A1

    公开(公告)日：2019-03-21

    申请号：US16128976

    申请日：2018-09-12

    Applicant: Integrated Device Technology, Inc.

    Inventor： Tumay Kanar ,  Chih-Hsiang Ko ,  Samet Zihir

    IPC: H01Q1/52 ,  H01Q1/48 ,  H01Q21/00 ,  H01Q21/06

    Abstract: An apparatus include a package and a beam former circuit. The package may be configured to be mounted on an antenna array at a center of four antenna elements. The beam former circuit may (i) be disposed in the package, (ii) have a plurality of ports, (iii) be configured to generate a plurality of radio-frequency signals in the ports while in a transmit mode and (iv) be configured to receive the radio-frequency signals at the ports while in a receive mode. A plurality of ground bumps may be disposed between the beam former circuit and the package. The ground bumps may be positioned to bracket each port. Each ground bump may be electrically connected to a signal ground to create a radio-frequency shielding between neighboring ports.

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