Transmit-receive switch with integrated power detection

    公开(公告)号:US10536186B1

    公开(公告)日:2020-01-14

    申请号:US16354650

    申请日:2019-03-15

    Abstract: An apparatus includes a plurality of impedance matching networks, a common port, a first switch circuit and a second switch circuit. The impedance matching networks may be (i) connected in series between an input port and an output port and (ii) configured to generate a power detection signal in response to a radio-frequency signal. The radio-frequency signal may be a transmit signal or a receive signal. The common port may be (i) connected to the impedance matching networks and (ii) connectable to an antenna. The first switch circuit may be configured to switch the input port and a circuit ground potential. The second switch circuit may be configured to switch the output port and the circuit ground potential.

    METHOD TO BUILD FAST TRANSMIT-RECEIVE SWITCHING ARCHITECTURE

    公开(公告)号:US20190089402A1

    公开(公告)日:2019-03-21

    申请号:US16131259

    申请日:2018-09-14

    Abstract: An apparatus includes a phased array antenna panel and one or more beam former circuits. The phased array antenna panel generally comprises a plurality of antenna elements. The plurality of antenna elements are generally arranged in one or more groups. The one or more beam former circuits may be mounted on the phased array antenna panel. Each beam former circuit is generally coupled to a respective group of the antenna elements. Each beam former circuit generally comprises a plurality of transceiver channels comprising a transmit channel and a receive channel. The phased array antenna panel is generally configured to distribute a control signal to each of the beam former circuits. Each of the transceiver channels is generally configured to switch between a transmit mode and a receive mode in response to the control signal.

    FAST MEMORY ACCESS CONTROL FOR PHASE AND GAIN

    公开(公告)号:US20190089399A1

    公开(公告)日:2019-03-21

    申请号:US16100408

    申请日:2018-08-10

    Abstract: An apparatus includes a switching circuit and a plurality of registers. The switching circuit may be configured to generate a sequence of pulses in a plurality of control signals in response to a plurality of cycles of an enable signal. The registers may be hardwired as a plurality of subsets. Each of the subsets of the registers may be configured to (a) buffer a plurality of setting values received from a memory and (b) present the setting values from the registers to a plurality of transceiver circuits while a corresponding one of the control signals is in an active state.The transceiver circuits may be updated with the setting values from the registers within a predetermined time.

    METHOD FOR SEPARATELY BIASING POWER AMPLIFIER FOR ADDITIONAL POWER CONTROL

    公开(公告)号:US20190089070A1

    公开(公告)日:2019-03-21

    申请号:US16132877

    申请日:2018-09-17

    Abstract: An apparatus includes a phased array antenna panel and one or more beam former circuits mounted on the phased array antenna panel. The phased array antenna panel generally comprises a plurality of antenna elements. The plurality of antenna elements are generally arranged in one or more groups. Each beam former circuit may be coupled to a respective group of the antenna elements. Each beam former circuit generally comprises a plurality of transceiver channels. Each transceiver channel generally comprises a power amplifier circuit configured, when operating in a transmit mode, to drive a respective one of the antenna elements. The power amplifier circuit generally comprises separate bias and voltage supply inputs providing additional power control.

    HARD-WIRED ADDRESS FOR PHASED ARRAY ANTENNA PANELS

    公开(公告)号:US20190089067A1

    公开(公告)日:2019-03-21

    申请号:US16121891

    申请日:2018-09-05

    Abstract: An apparatus includes a phased array antenna panel and a plurality of beam former circuits. The phased array antenna panel generally comprises a plurality of antenna elements. The plurality of beam former circuits are each mounted on the phased array antenna panel adjacent to a number of the antenna elements. Each beam former circuit has one or more ports directly coupled to each of the adjacent antenna elements. Each beam former circuit may be configured to generate a plurality of radio-frequency output signals at the ports while in a transmit mode and receive a plurality of radio-frequency input signals at the ports while in a receive mode. Each beam former circuit generally implements a hard-wired address.

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