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    PHY RECALIBRATION USING A MESSAGE BUS INTERFACE
    31.
    发明申请
    PHY RECALIBRATION USING A MESSAGE BUS INTERFACE 审中-公开

    公开(公告)号：US20190303342A1

    公开(公告)日：2019-10-03

    申请号：US16446470

    申请日：2019-06-19

    Applicant: Intel Corporation

    Inventor： Michelle C. Jen ,  Minxi Gao ,  Debendra Das Sharma ,  Fulvio Spagna ,  Bruce A. Tennant ,  Noam Dolev Geldbard

    IPC: G06F13/42

    Abstract: An interface couples a controller to a physical layer (PHY) block, where the interface includes a set of data pins comprising transmit data pins to send data to the PHY block and receive data pins to receive data from the PHY block. The interface further includes a particular set of pins to implement a message bus interface, where the controller is to send a write command to the PHY block over the message bus interface to write a value to at least one particular bit of a PHY message bus register, bits of the PHY message bus register are mapped to a set of control and status signals, and the particular bit is mapped to a recalibration request signal to request that the PHY block perform a recalibration.

    FLEX BUS PROTOCOL NEGOTIATION AND ENABLING SEQUENCE
    35.
    发明申请
    FLEX BUS PROTOCOL NEGOTIATION AND ENABLING SEQUENCE 审中-公开

    公开(公告)号：US20190065426A1

    公开(公告)日：2019-02-28

    申请号：US16171342

    申请日：2018-10-25

    Applicant: Intel Corporation

    Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Prahladachar Jayaprakash Bharadwaj ,  Bruce A. Tennant ,  Mahesh Wagh

    IPC: G06F13/40 ,  G06F13/42

    Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

    CONNECTING ACCELERATOR RESOURCES USING A SWITCH
    36.
    发明申请
    CONNECTING ACCELERATOR RESOURCES USING A SWITCH 审中-公开

    公开(公告)号：US20190065272A1

    公开(公告)日：2019-02-28

    申请号：US15682896

    申请日：2017-08-22

    Applicant: Intel Corporation

    Inventor： Anil Rao ,  Debendra Das Sharma

    IPC: G06F9/50 ,  G06F9/48 ,  G06F9/44 ,  H04L29/08

    Abstract: The present disclosure describes a number of embodiments related to devices and techniques for implementing an interconnect switch to provide a switchable low-latency bypass between node resources such as CPUs and accelerator resources for caching. A resource manager may be used to receive an indication of a node of a plurality of nodes and an indication of an accelerator resource of a plurality of accelerator resources to connect to the node. If the indicated accelerator resource is connected to another node of the plurality of nodes, then transmit, to a interconnect switch, one or more hot-remove commands. The resource manager may then transmit to the interconnect switch one or more hot-add commands to connect the node resource and the accelerator resource.

    LOW LATENCY MULTI-PROTOCOL RETIMERS
    39.
    发明申请
    LOW LATENCY MULTI-PROTOCOL RETIMERS 有权

    公开(公告)号：US20170371831A1

    公开(公告)日：2017-12-28

    申请号：US15193941

    申请日：2016-06-27

    Applicant: Intel Corporation

    Inventor： Debendra Das Sharma

    IPC: G06F13/42 ,  G06F13/40

    CPC classification number: G06F13/4291 ,  G06F13/4068

    Abstract: A multi-protocol retimer apparatus and method for using the same are disclosed. In one embodiment, an apparatus for performing retiming between first and second devices according to a plurality of protocols comprises: a receiver operable to receive data; a transmitter to transmit data; a first data path coupled to the receiver and the transmitter and operable to transfer data received from the receiver to the transmitter during protocol specific training, where the first data path comprises control circuitry to control protocol specific training of one or both of the transmitter and receiver in response to an indication of one protocol of the plurality of protocols; and a second data path coupled to the receiver and the transmitter, the second data path having a lower latency than the first data path and for use in transferring data received from the receiver to the transmitter after protocol specific training.

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