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    Bimodal phy for low latency in high speed interconnects
    2.
    发明授权
    Bimodal phy for low latency in high speed interconnects 有权

    公开(公告)号：US10599602B2

    公开(公告)日：2020-03-24

    申请号：US16446996

    申请日：2019-06-20

    Applicant: INTEL CORPORATION

    Inventor： Venkatraman Iyer ,  William R. Halleck ,  Rahul R. Shah ,  Eric Lee

    IPC: G06F13/40 ,  G06F13/38 ,  G06F13/42 ,  G06F13/16

    Abstract: Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.

    BIMODAL PHY FOR LOW LATENCY IN HIGH SPEED INTERCONNECTS
    3.
    发明申请
    BIMODAL PHY FOR LOW LATENCY IN HIGH SPEED INTERCONNECTS 审中-公开

    公开(公告)号：US20180181525A1

    公开(公告)日：2018-06-28

    申请号：US15390648

    申请日：2016-12-26

    Applicant: Intel Corporation

    Inventor： Venkatraman Iyer ,  William R. Halleck ,  Rahul R. Shah ,  Eric Lee

    IPC: G06F13/40 ,  G06F13/42 ,  G06F13/16

    CPC classification number: G06F13/4068 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/382 ,  G06F13/385 ,  G06F13/4282 ,  G06F2213/0026

    Abstract: Systems, methods, and apparatuses involve a PHY coupled to a MAC. The PHY can include a drift buffer coupled to an output of a receiver and a bypass branch coupled to the output of the receiver. The PHY includes a clocking multiplexer that includes a first clock input coupled to a recovered clock of the PHY and a second clock input coupled to a p-clock of the MAC; and a clock output configured to output one of the recovered clock or the p-clock based on a selection input value. The PHY includes a bypass multiplexer that includes a first data input coupled to an output of a drift buffer and a second data input coupled to the bypass branch; and a data output configured to output one of the output of the drift buffer or data from the bypass branch based on the section input value of the clocking multiplexer.

    LINK-PHYSICAL LAYER INTERFACE ADAPTER
    4.
    发明申请
    LINK-PHYSICAL LAYER INTERFACE ADAPTER 审中-公开

    公开(公告)号：US20180095923A1

    公开(公告)日：2018-04-05

    申请号：US15283309

    申请日：2016-10-01

    Applicant: Intel Corporation

    Inventor： Venkatraman Iyer ,  Mahesh Wagh ,  William R. Halleck ,  Rahul R. Shah

    IPC: G06F13/40 ,  G06F13/36 ,  G06F13/42

    CPC classification number: G06F13/4068 ,  G06F13/36 ,  G06F13/4022 ,  G06F13/4027 ,  G06F13/4265 ,  G11C27/04

    Abstract: An interface adapter to identify a first ready signal from a first link layer-to-physical layer (LL-PHY) interface of a first communication protocol indicating readiness of a physical layer of the first protocol to accept link layer data. The interface adapter generates a second ready signal compatible with a second LL-PHY interface of a second communication protocol to cause link layer data to be sent from a link layer of the second communication protocol according to a predefined delay. A third ready signal is generated compatible with the first LL-PHY interface to indicate to the physical layer of the first communication protocol that the link layer data is to be sent. The interface adapter uses a shift register to cause the link layer data to be passed to the physical layer according to the predefined delay.

    Bimodal PHY for low latency in high speed interconnects
    5.
    发明授权
    Bimodal PHY for low latency in high speed interconnects 有权

    公开(公告)号：US11354264B2

    公开(公告)日：2022-06-07

    申请号：US17184737

    申请日：2021-02-25

    Applicant: Intel Corporation

    Inventor： Venkatraman Iyer ,  William R. Halleck ,  Rahul R. Shah ,  Eric Lee

    IPC: G06F13/40 ,  G06F13/38 ,  G06F13/42 ,  G06F13/16

    Abstract: Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.

    Link-physical layer interface adapter
    8.
    发明授权
    Link-physical layer interface adapter 有权

    公开(公告)号：US10152446B2

    公开(公告)日：2018-12-11

    申请号：US15283309

    申请日：2016-10-01

    Applicant: Intel Corporation

    Inventor： Venkatraman Iyer ,  Mahesh Wagh ,  William R. Halleck ,  Rahul R. Shah

    IPC: G06F13/38 ,  G06F13/36 ,  G06F13/40 ,  G06F13/42 ,  G11C27/04

    Abstract: An interface adapter to identify a first ready signal from a first link layer-to-physical layer (LL-PHY) interface of a first communication protocol indicating readiness of a physical layer of the first protocol to accept link layer data. The interface adapter generates a second ready signal compatible with a second LL-PHY interface of a second communication protocol to cause link layer data to be sent from a link layer of the second communication protocol according to a predefined delay. A third ready signal is generated compatible with the first LL-PHY interface to indicate to the physical layer of the first communication protocol that the link layer data is to be sent. The interface adapter uses a shift register to cause the link layer data to be passed to the physical layer according to the predefined delay.

    Packet processing load balancer
    10.
    发明授权
    Packet processing load balancer 有权

    公开(公告)号：US12293231B2

    公开(公告)日：2025-05-06

    申请号：US17471889

    申请日：2021-09-10

    Applicant: Intel Corporation

    Inventor： Chenmin Sun ,  Yipeng Wang ,  Rahul R. Shah ,  Ren Wang ,  Sameh Gobriel ,  Hongjun Ni ,  Mrittika Ganguli ,  Edwin Verplanke

    IPC: G06F9/50 ,  H04L47/11 ,  H04L47/12 ,  H04L47/125 ,  H04L12/70

    Abstract: Examples described herein include a device interface; a first set of one or more processing units; and a second set of one or more processing units. In some examples, the first set of one or more processing units are to perform heavy flow detection for packets of a flow and the second set of one or more processing units are to perform processing of packets of a heavy flow. In some examples, the first set of one or more processing units and second set of one or more processing units are different. In some examples, the first set of one or more processing units is to allocate pointers to packets associated with the heavy flow to a first set of one or more queues of a load balancer and the load balancer is to allocate the packets associated with the heavy flow to one or more processing units of the second set of one or more processing units based, at least in part on a packet receive rate of the packets associated with the heavy flow.

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