公开(公告)号：US10955899B2

公开(公告)日：2021-03-23

申请号：US16013142

申请日：2018-06-20

Applicant: Intel Corporation

Inventor： Hisham Abu Salah ,  Efraim Rotem ,  Eliezer Weissmann ,  Yoni Aizik ,  Daniel D. Lederman

IPC: G06F1/32 ,  G06F1/324 ,  G06F1/3296 ,  G06F1/3206

Abstract: In one embodiment, processor includes a first core to execute instructions, and a power controller to control power consumption of the processor. The power controller may include a hardware performance state controller to control a performance state of the first core autonomously to an operating system, and calculate a target operating frequency for the performance state based at least in part on an energy performance preference hint received from the operating system. Other embodiments are described and claimed.

公开(公告)号：US20210026708A1

公开(公告)日：2021-01-28

申请号：US16523009

申请日：2019-07-26

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Hisham Abu-Salah ,  Nir Rosenzweig ,  Efraim Rotem

IPC: G06F9/50 ,  G06F1/324 ,  G06F1/08

Abstract: A processor comprises multiple cores and power management control logic to determine (a) a preliminary frequency for each of the cores and (b) a maximum frequency, based on the preliminary frequencies. The power management control logic is also to determines a dynamic tuning frequency, based on the maximum frequency and a reduction factor. In response to the dynamic tuning frequency for a selected core being greater than the preliminary frequency for that core, the power management control logic is to set the core to a frequency that is at least equal to the dynamic tuning frequency. In response to the preliminary frequency for the selected core being greater than the dynamic tuning frequency for that core, the power management control logic is to set the core to a frequency that is at least equal to the preliminary frequency. Other embodiments are described and claimed.

公开(公告)号：US10884483B2

公开(公告)日：2021-01-05

申请号：US16130916

申请日：2018-09-13

Applicant: Intel Corporation

Inventor： Jawad Haj-Yihia ,  Eliezer Weissmann ,  Vijay S. R. Degalahal ,  Nadav Shulman ,  Tal Kuzi ,  Itay Franko ,  Amit Gur ,  Efraim Rotem

IPC: G06F1/00 ,  G06F1/3287 ,  G06F1/3234

Abstract: Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency. are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.

公开(公告)号：US10705588B2

公开(公告)日：2020-07-07

申请号：US16249103

申请日：2019-01-16

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Inder M. Sodhi ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Ryan Wells

IPC: G06F1/324 ,  G06F1/3293 ,  G06F1/3203 ,  G11C7/22 ,  G06F13/42 ,  G06F1/3296 ,  G06F13/40

Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.

公开(公告)号：US20200210184A1

公开(公告)日：2020-07-02

申请号：US16233297

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Hisham Abu-Salah ,  Daniel Lederman ,  Nir Rosenzweig ,  Efraim Rotem ,  Esfir Natanzon ,  Yevgeni Sabin ,  Shay Levy

IPC: G06F9/30 ,  G06F1/3234 ,  G06F1/329

Abstract: In an embodiment, a processor for demotion includes a plurality of cores to execute instructions and a demotion control circuit. The demotion control circuit is to: for each core of the plurality of cores, determine an average count of power state break events in the core; determine a sum of the average counts of the plurality of cores; determine whether the average count of a first core exceeds a first demotion threshold; determine whether the sum of the average counts of the plurality of cores exceeds a second demotion threshold; and in response to a determination that the average count of the first core exceeds the first demotion threshold and the sum of the average counts exceeds the second demotion threshold, perform a power state demotion of the first core. Other embodiments are described and claimed.

公开(公告)号：US20200057480A1

公开(公告)日：2020-02-20

申请号：US16663645

申请日：2019-10-25

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

IPC: G06F1/324 ,  G06F1/3296

Abstract: In one embodiment, a processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator. Other embodiments are described and claimed.

公开(公告)号：US10467012B2

公开(公告)日：2019-11-05

申请号：US15394458

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Karthikeyan Karthik Vaithianathan ,  Yoav Zach ,  Boris Ginzburg ,  Ronny Ronen

IPC: G06F9/38 ,  G06F12/1027 ,  G06F12/1009 ,  G06F12/1081 ,  G06F12/1072 ,  G06F12/0875 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/1045 ,  G06F3/06 ,  G06F12/02 ,  G06F12/14

Abstract: An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

公开(公告)号：US10379904B2

公开(公告)日：2019-08-13

申请号：US15252511

申请日：2016-08-31

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Israel Hirsh ,  Efraim Rotem ,  Doron Rajwan ,  Avinash N. Ananthakrishnan ,  Natanel Abitan ,  Ido Melamed ,  Guy M. Therien

IPC: G06F9/46 ,  G06F1/32 ,  G06F9/48 ,  G06F9/50

Abstract: In one embodiment, a processor includes: a first storage to store a set of common performance state request settings; a second storage to store a set of thread performance state request settings; and a controller to control a performance state of a first core based on a combination of at least one of the set of common performance state request settings and at least one of the set of thread performance state request settings. Other embodiments are described and claimed.

公开(公告)号：US20190235611A1

公开(公告)日：2019-08-01

申请号：US16382320

申请日：2019-04-12

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Hisham Abu-Salah

IPC: G06F1/3234 ,  G06F12/0802 ,  G06F12/0864 ,  G06F1/28 ,  G06F12/084 ,  G06F1/3287 ,  G06F12/0846

CPC classification number: G06F1/3275 ,  G06F1/28 ,  G06F1/3287 ,  G06F12/0802 ,  G06F12/084 ,  G06F12/0848 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/282 ,  G06F2212/502 ,  G06F2212/621 ,  Y02D10/13

Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

公开(公告)号：US10127039B2

公开(公告)日：2018-11-13

申请号：US15175881

申请日：2016-06-07

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Michael Mishaeli ,  Boris Ginzburg ,  Alon Naveh

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46

Abstract: A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. A save instruction is executed to store a micro-architectural state and an architectural state of a processor in a common buffer of a memory upon a context switch that suspends the execution of a process. The micro-architectural state contains performance data resulting from the execution of the process. A restore instruction is executed to retrieve the micro-architectural state and the architectural state from the common buffer upon a resumed execution of the process. Power management hardware then uses the micro-architectural state as an intermediate starting point for the resumed execution.