公开(公告)号：US20170371400A1

公开(公告)日：2017-12-28

申请号：US15686222

申请日：2017-08-25

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Efraim Rotem ,  Hisham Abu Salah ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Gal Leibovich ,  Yevgeni Sabin ,  Shay Levy

IPC: G06F1/32 ,  G06F9/50

CPC classification number: G06F1/3287 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/22

Abstract: In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.

公开(公告)号：US09760160B2

公开(公告)日：2017-09-12

申请号：US14722518

申请日：2015-05-27

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Efraim Rotem ,  Hisham Abu Salah ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Gal Leibovich ,  Yevgeni Sabin ,  Shay Levy

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/00 ,  G06F9/50

CPC classification number: G06F1/3287 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/172

Abstract: In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.

公开(公告)号：US10372198B2

公开(公告)日：2019-08-06

申请号：US15686222

申请日：2017-08-25

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Efraim Rotem ,  Hisham Abu Salah ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Gal Leibovich ,  Yevgeni Sabin ,  Shay Levy

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/00 ,  G06F1/3287 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/3296 ,  G06F9/50

Abstract: In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.

公开(公告)号：US20160349828A1

公开(公告)日：2016-12-01

申请号：US14722518

申请日：2015-05-27

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Efraim Rotem ,  Hisham Abu Salah ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Gal Leibovich ,  Yevgeni Sabin ,  Shay Levy

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/172

Abstract: In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括：多个处理引擎，包括独立执行指令的第一处理引擎和第二处理引擎; 以及功率控制器，其包括用于控制所述处理引擎中的至少一个的性能状态的性能状态控制逻辑，以及用于在第一窗口中确定所述主动处理引擎的平均数量的第一逻辑，所述处理器的估计活动级别 并且至少部分地基于所估计的活动级别和所述第一窗口的比较来调整所述性能状态控制逻辑将执行性能状态确定和至少一个活动级别阈值的窗口长度中的至少一个 平均主动处理引擎数。 描述和要求保护其他实施例。

公开(公告)号：US11216276B2

公开(公告)日：2022-01-04

申请号：US16233297

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Hisham Abu-Salah ,  Daniel Lederman ,  Nir Rosenzweig ,  Efraim Rotem ,  Esfir Natanzon ,  Yevgeni Sabin ,  Shay Levy

IPC: G06F9/30 ,  G06F1/3234 ,  G06F1/329 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3203 ,  G06F1/3287

Abstract: In an embodiment, a processor for demotion includes a plurality of cores to execute instructions and a demotion control circuit. The demotion control circuit is to: for each core of the plurality of cores, determine an average count of power state break events in the core; determine a sum of the average counts of the plurality of cores; determine whether the average count of a first core exceeds a first demotion threshold; determine whether the sum of the average counts of the plurality of cores exceeds a second demotion threshold; and in response to a determination that the average count of the first core exceeds the first demotion threshold and the sum of the average counts exceeds the second demotion threshold, perform a power state demotion of the first core. Other embodiments are described and claimed.

公开(公告)号：US20200210184A1

公开(公告)日：2020-07-02

申请号：US16233297

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Hisham Abu-Salah ,  Daniel Lederman ,  Nir Rosenzweig ,  Efraim Rotem ,  Esfir Natanzon ,  Yevgeni Sabin ,  Shay Levy

IPC: G06F9/30 ,  G06F1/3234 ,  G06F1/329

Abstract: In an embodiment, a processor for demotion includes a plurality of cores to execute instructions and a demotion control circuit. The demotion control circuit is to: for each core of the plurality of cores, determine an average count of power state break events in the core; determine a sum of the average counts of the plurality of cores; determine whether the average count of a first core exceeds a first demotion threshold; determine whether the sum of the average counts of the plurality of cores exceeds a second demotion threshold; and in response to a determination that the average count of the first core exceeds the first demotion threshold and the sum of the average counts exceeds the second demotion threshold, perform a power state demotion of the first core. Other embodiments are described and claimed.