公开(公告)号：US20190287973A1

公开(公告)日：2019-09-19

申请号：US16430203

申请日：2019-06-03

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid M. Hafez ,  Jeng-Ya David Yeh ,  Hsu-Yu Chang ,  Neville L. Dias ,  Chanaka D. Munasinghe

IPC: H01L27/092 ,  H01L29/10 ,  H01L29/08 ,  H01L21/225 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area.

公开(公告)号：US20170207312A1

公开(公告)日：2017-07-20

申请号：US15327641

申请日：2014-08-19

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid Hafez ,  Hsu-Yu Chang ,  Roman Olac-Vaw ,  Ting Chang ,  Rahul Ramaswamy ,  Pei-Chi Liu ,  Neville Dias

IPC: H01L29/423 ,  H01L23/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L23/535

CPC classification number: H01L29/42376 ,  H01L21/28088 ,  H01L21/31155 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823475 ,  H01L23/535 ,  H01L23/66 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/78

Abstract: Semiconductor device(s) including a transistor with a gate electrode having a work function monotonically graduating across the gate electrode length, and method(s) to fabricate such a device. In embodiments, a gate metal work function is graduated between source and drain edges of the gate electrode for improved high voltage performance. In embodiments, thickness of a gate metal graduates from a non-zero value at the source edge to a greater thickness at the drain edge. In further embodiments, a high voltage transistor with graduated gate metal thickness is integrated with another transistor employing a gate electrode metal of nominal thickness. In embodiments, a method of fabricating a semiconductor device includes graduating a gate metal thickness between a source end and drain end by non-uniformly recessing the first gate metal within the first opening relative to the surrounding dielectric.