公开(公告)号：US12086120B2

公开(公告)日：2024-09-10

申请号：US18066436

申请日：2022-12-15

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Abhishek R. Appu ,  Karol Szerszen ,  Eric Liskay ,  Karthik Vaidyanathan

IPC: G06F16/22 ,  G06N20/00 ,  G06T1/20

CPC classification number: G06F16/2237 ,  G06N20/00 ,  G06T1/20

Abstract: Embodiments are generally directed to compression for compression for sparse data structures utilizing mode search approximation. An embodiment of an apparatus includes one or more processors including a graphics processor to process data; and a memory for storage of data, including compressed data. The one or more processors are to provide for compression of a data structure, including identification of a mode in the data structure, the data structure including a plurality of values and the mode being a most repeated value in a data structure, wherein identification of the mode includes application of a mode approximation operation, and encoding of an output vector to include the identified mode, a significance map to indicate locations at which the mode is present in the data structure, and remaining uncompressed data from the data structure.

公开(公告)号：US20240257433A1

公开(公告)日：2024-08-01

申请号：US18414841

申请日：2024-01-17

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Abhishek R. Appu ,  Karthik Vaidyanathan ,  Saikat Mandal ,  Michael Norris

IPC: G06T15/00 ,  G06F3/06 ,  G06T15/06

CPC classification number: G06T15/005 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06T15/06

Abstract: Apparatus and method for asynchronous ray tracing. For example, one embodiment of a processor comprises: a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged nodes including a root node, a plurality of internal nodes, and a plurality of leaf nodes comprising primitives, wherein each internal node comprises a child node to either the root node or another internal node and each leaf node comprises a child node to an internal node; a first storage bank to be arranged as a first plurality of entries; a second storage bank to be arranged as a second plurality of entries, wherein each entry of the first plurality of entries and the second plurality of entries is to store a ray to be traversed through the BVH; an allocator circuit to distribute an incoming ray to either the first storage bank or the second storage bank based on a relative numbers of rays currently stored in the first and second storage banks; and traversal circuitry to alternate between selecting a next ray from the first storage bank and the second storage bank, the traversal circuitry to traverse the next ray through the BVH by reading a next BVH node from a top of a BVH node stack and determining whether the next ray intersects the next BVH node.

公开(公告)号：US11989817B2

公开(公告)日：2024-05-21

申请号：US17349602

申请日：2021-06-16

Applicant: Intel Corporation

Inventor： Holger Gruen ,  Karthik Vaidyanathan

IPC: G06T15/06 ,  G06T15/00

CPC classification number: G06T15/06 ,  G06T15/005 ,  G06T2210/36

Abstract: Apparatus and method for more precise level-of-details transitions. For example one embodiment includes a graphics processor comprising: ray traversal hardware logic to traverse a ray through an acceleration structure to determine intersections between the ray and one or more object instances; and a level of detail selector to: set an instance comparison mask associated with an object instance to a first level of detail (LOD), the instance comparison mask comprising an N-bit value and one or more bits to indicate a type of comparison operation, compare a value from a ray mask with the N-bit value in accordance with the type of comparison operation to generate a comparison result, and determine whether to use the first LOD or a second LOD to render one or more pixels in accordance with the comparison result.

公开(公告)号：US11915357B2

公开(公告)日：2024-02-27

申请号：US16820483

申请日：2020-03-16

Applicant: Intel Corporation

Inventor： Karthik Vaidyanathan ,  Abhishek Appu ,  Vasanth Ranganathan ,  Joydeep Ray ,  Prasoonkumar Surti

IPC: G06T15/06 ,  G06T15/00

CPC classification number: G06T15/005 ,  G06T15/06

Abstract: Apparatus and method for stack throttling. For example, one embodiment of an apparatus comprises: execution circuitry comprising a plurality of functional units to execute a plurality of ray shaders and generate a plurality of primary rays and a corresponding plurality of ray messages; a first in first out (FIFO) buffer to queue the ray messages generated by the EUs; a cache to store one or more of the plurality of primary rays; a memory-backed stack to store a first subset of the plurality of ray messages in a corresponding plurality of entries; memory-backed stack management circuitry to either store a second subset of the plurality of ray messages to the memory-backed stack, or to temporarily store the one or more the second subset of the plurality of ray messages to a memory subsystem based, at least in part, on a number of entries currently occupied by ray messages in the memory-backed stack; and ray traversal circuitry to read a next ray message from the memory-backed stack, retrieve a next primary ray identified by the ray message from the cache or a memory subsystem, and perform traversal operations on the next primary ray.

公开(公告)号：US20230252010A1

公开(公告)日：2023-08-10

申请号：US18066436

申请日：2022-12-15

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Abhishek R. Appu ,  Karol Szerszen ,  Eric Liskay ,  Karthik Vaidyanathan

IPC: G06F16/22 ,  G06N20/00 ,  G06T1/20

CPC classification number: G06F16/2237 ,  G06N20/00 ,  G06T1/20

Abstract: Embodiments are generally directed to compression for compression for sparse data structures utilizing mode search approximation. An embodiment of an apparatus includes one or more processors including a graphics processor to process data; and a memory for storage of data, including compressed data. The one or more processors are to provide for compression of a data structure, including identification of a mode in the data structure, the data structure including a plurality of values and the mode being a most repeated value in a data structure, wherein identification of the mode includes application of a mode approximation operation, and encoding of an output vector to include the identified mode, a significance map to indicate locations at which the mode is present in the data structure, and remaining uncompressed data from the data structure.

公开(公告)号：US11663774B2

公开(公告)日：2023-05-30

申请号：US17684686

申请日：2022-03-02

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06T15/50 ,  G06T15/00 ,  G06T15/80 ,  G06T17/20

CPC classification number: G06T15/503 ,  G06T15/005 ,  G06T15/80 ,  G06T17/205 ,  G06T2200/12

Abstract: Systems, apparatuses and methods may provide away to render edges of an object defined by multiple tessellation triangles. More particularly, systems, apparatuses and methods may provide a way to perform anti-aliasing at the edges of the object based on a coarse pixel rate, where the coarse pixels may be based on a coarse Z value indicate a resolution or granularity of detail of the coarse pixel. The systems, apparatuses and methods may use a shader dispatch engine to dispatch raster rules to a pixel shader to direct the pixel shader to include, in a tile and/or tessellation triangle, one more finer coarse pixels based on a percent of coverage provided by a finer coarse pixel of a tessellation triangle at or along the edge of the object.

公开(公告)号：US11574382B2

公开(公告)日：2023-02-07

申请号：US17466591

申请日：2021-09-03

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Eric G. Liskay ,  Prasoonkumar Surti ,  Sudhakar Kamma ,  Karthik Vaidyanathan ,  Rajasekhar Pantangi ,  Altug Koker ,  Abhishek Rhisheekesan ,  Shashank Lakshminarayana ,  Priyanka Ladda ,  Karol A. Szerszen

IPC: G06T1/60 ,  G06T1/20 ,  G06F9/50 ,  G06F9/38

Abstract: Examples described herein relate to a decompression engine that can request compressed data to be transferred over a memory bus. In some cases, the memory bus is a width that requires multiple data transfers to transfer the requested data. In a case that requested data is to be presented in-order to the decompression engine, a re-order buffer can be used to store entries of data. When a head-of-line entry is received, the entry can be provided to the decompression engine. When a last entry in a group of one or more entries is received, all entries in the group are presented in-order to the decompression engine. In some examples, a decompression engine can borrow memory resources allocated for use by another memory client to expand a size of re-order buffer available for use. For example, a memory client with excess capacity and a slowest growth rate can be chosen to borrow memory resources from.

公开(公告)号：US20220262059A1

公开(公告)日：2022-08-18

申请号：US17591166

申请日：2022-02-02

Applicant: Intel Corporation

Inventor： Devan Burke ,  Adam T. Lake ,  Jeffery S. Boles ,  John H. Feit ,  Karthik Vaidyanathan ,  Abhishek R. Appu ,  Joydeep Ray ,  Subramaniam Maiyuran ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Prasoonkumar Surti ,  Eric J. Hoekstra ,  Gabor Liktor ,  Jonathan Kennedy ,  Slawomir Grajewski ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06T15/00 ,  G06F9/48

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.

公开(公告)号：US20220172316A1

公开(公告)日：2022-06-02

申请号：US17486330

申请日：2021-09-27

Applicant: Intel Corporation

Inventor： Abhishek Venkatesh ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Prasoonkumar Surti

IPC: G06T1/20 ,  G06F9/30 ,  G06F9/38 ,  G06T15/00

Abstract: An embodiment of a graphics command coordinator apparatus may include a commonality identifier to identify a commonality between a first graphics command corresponding to a first frame and a second graphics command corresponding to a second frame, a commonality analyzer communicatively coupled to the commonality identifier to determine if the first graphics command and the second graphics command can be processed together based on the commonality identified by the commonality identifier, and a commonality indicator communicatively coupled to the commonality analyzer to provide an indication that the first graphics command and the second graphics command are to be processed together. Other embodiments are disclosed and claimed.

公开(公告)号：US11348198B2

公开(公告)日：2022-05-31

申请号：US17145885

申请日：2021-01-11

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F9/455 ,  G06F9/50 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06F8/41

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of execution units (EUs), wherein the plurality of EUs comprise a first EU type and a second EU type.