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公开(公告)号：US20240211403A1
公开(公告)日：2024-06-27
申请号：US18086441
申请日：2022-12-21
Applicant: Intel Corporation
Inventor： Abhishek R. Appu , Joydeep Ray , Karthik Vaidyanathan , Sreedhar Chalasani , Eric Liskay , Prathamesh Raghunath Shinde , Vasanth Ranganathan , Michael J. Norris , Rajasekhar Pantangi , Altug Koker
IPC: G06F12/0837 , G06F12/0811
CPC classification number: G06F12/0837 , G06F12/0811
Abstract: One embodiment provides a graphics processor comprising memory access circuitry configured to generate a virtual address for pixel data at a pixel coordinate on a surface in memory to facilitate the caching of the pixel data in a cache memory before the actual memory address of the pixel coordinate is able to be determined.
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公开(公告)号：US12086120B2
公开(公告)日：2024-09-10
申请号：US18066436
申请日：2022-12-15
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Abhishek R. Appu , Karol Szerszen , Eric Liskay , Karthik Vaidyanathan
CPC classification number: G06F16/2237 , G06N20/00 , G06T1/20
Abstract: Embodiments are generally directed to compression for compression for sparse data structures utilizing mode search approximation. An embodiment of an apparatus includes one or more processors including a graphics processor to process data; and a memory for storage of data, including compressed data. The one or more processors are to provide for compression of a data structure, including identification of a mode in the data structure, the data structure including a plurality of values and the mode being a most repeated value in a data structure, wherein identification of the mode includes application of a mode approximation operation, and encoding of an output vector to include the identified mode, a significance map to indicate locations at which the mode is present in the data structure, and remaining uncompressed data from the data structure.
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Patent Agency Ranking
公开(公告)号：US20230252010A1
公开(公告)日：2023-08-10
申请号：US18066436
申请日：2022-12-15
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Abhishek R. Appu , Karol Szerszen , Eric Liskay , Karthik Vaidyanathan
CPC classification number: G06F16/2237 , G06N20/00 , G06T1/20
Abstract: Embodiments are generally directed to compression for compression for sparse data structures utilizing mode search approximation. An embodiment of an apparatus includes one or more processors including a graphics processor to process data; and a memory for storage of data, including compressed data. The one or more processors are to provide for compression of a data structure, including identification of a mode in the data structure, the data structure including a plurality of values and the mode being a most repeated value in a data structure, wherein identification of the mode includes application of a mode approximation operation, and encoding of an output vector to include the identified mode, a significance map to indicate locations at which the mode is present in the data structure, and remaining uncompressed data from the data structure.
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公开(公告)号：US20200311041A1
公开(公告)日：2020-10-01
申请号：US16371342
申请日：2019-04-01
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Abhishek R. Appu , Karol Szerszen , Eric Liskay , Karthik Vaidyanathan
Abstract: Embodiments are generally directed to compression for compression for sparse data structures utilizing mode search approximation. An embodiment of an apparatus includes one or more processors including a graphics processor to process data; and a memory for storage of data, including compressed data. The one or more processors are to provide for compression of a data structure, including identification of a mode in the data structure, the data structure including a plurality of values and the mode being a most repeated value in a data structure, wherein identification of the mode includes application of a mode approximation operation, and encoding of an output vector to include the identified mode, a significance map to indicate locations at which the mode is present in the data structure, and remaining uncompressed data from the data structure.
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公开(公告)号：US20250036608A1
公开(公告)日：2025-01-30
申请号：US18796619
申请日：2024-08-07
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Abhishek R. Appu , Karol Szerszen , Eric Liskay , Karthik Vaidyanathan
Abstract: Embodiments are generally directed to compression for compression for sparse data structures utilizing mode search approximation. An embodiment of an apparatus includes one or more processors including a graphics processor to process data; and a memory for storage of data, including compressed data. The one or more processors are to provide for compression of a data structure, including identification of a mode in the data structure, the data structure including a plurality of values and the mode being a most repeated value in a data structure, wherein identification of the mode includes application of a mode approximation operation, and encoding of an output vector to include the identified mode, a significance map to indicate locations at which the mode is present in the data structure, and remaining uncompressed data from the data structure.
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公开(公告)号：US20240281249A1
公开(公告)日：2024-08-22
申请号：US18170808
申请日：2023-02-17
Applicant: Intel Corporation
Inventor： Abhishek R. Appu , Altug Koker , Joydeep Ray , Karthik Vaidyanathan , Sreedhar Chalasani , Eric Liskay , Prathamesh Raghunath Shinde , Vasanth Ranganathan , Michael J. Norris , Rajasekhar Pantangi
CPC classification number: G06F9/30043 , G06F9/30047 , G06F9/546
Abstract: One embodiment provides a graphics processor comprising memory access circuitry configured to receive a message from an instruction execution resource and determine a destination for the message, the destination one of shared function circuitry of a graphics core or a set of memory banks within the graphics core. The memory access circuitry then routes the message to the shared function circuitry in response to a determination that the message is directed to the shared function circuitry or routes the message to a message sequencer associated with the instruction execution resource in response to a determination that the message is directed to the set of memory banks.
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公开(公告)号：US11556511B2
公开(公告)日：2023-01-17
申请号：US16371342
申请日：2019-04-01
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Abhishek R. Appu , Karol Szerszen , Eric Liskay , Karthik Vaidyanathan
Abstract: Embodiments are generally directed to compression for compression for sparse data structures utilizing mode search approximation. An embodiment of an apparatus includes one or more processors including a graphics processor to process data; and a memory for storage of data, including compressed data. The one or more processors are to provide for compression of a data structure, including identification of a mode in the data structure, the data structure including a plurality of values and the mode being a most repeated value in a data structure, wherein identification of the mode includes application of a mode approximation operation, and encoding of an output vector to include the identified mode, a significance map to indicate locations at which the mode is present in the data structure, and remaining uncompressed data from the data structure.
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