公开(公告)号：US11411491B2

公开(公告)日：2022-08-09

申请号：US16642853

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Vivek De ,  Krishnan Ravichandran ,  Harish Krishnamurthy ,  Khondker Ahmed ,  Sriram Vangal ,  Vaibhav Vaidya ,  Turbo Majumder ,  Christopher Schaef ,  Suhwan Kim ,  Xiaosen Liu ,  Nachiket Desai

IPC: H02M3/158 ,  H02M3/07 ,  H02M1/00

Abstract: Voltage dividing circuitry is provided for use in a voltage converter for converting at least one input Direct Current, DC voltage to a plurality of output DC voltages. The voltage dividing circuitry including a voltage input port to receive an input DC voltage and an inductor having an input-side switch node and an output-side switch node. The output side switch node is connectable to one of a plurality of voltage output ports to supply a converted value of the input DC voltage as an output DC voltage. The flying capacitor interface has a plurality of switching elements and at least one flying capacitor, the flying capacitor interface to divide the input DC voltage to provide a predetermined fixed ratio of the input DC voltage at the input-side switch node of the inductor. A voltage converter and a power management integrated circuit having the voltage dividing circuitry are also provided.

公开(公告)号：US20190190725A1

公开(公告)日：2019-06-20

申请号：US15846045

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Vivek De ,  Krishnan Ravichandran ,  Harish Krishnamurthy ,  Khondker Ahmed ,  Sriram Vangal ,  Vaibhav Vaidya ,  Turbo Majumder ,  Christopher Schaef ,  Suhwan Kim ,  Xiaosen Liu ,  Nachiket Desai

IPC: H04L9/32

CPC classification number: H04L9/3278

Abstract: An apparatus is provided which comprises: an array of physically unclonable function (PUF) devices, wherein an individual device of the array comprises a magnetic junction and an interconnect, wherein the interconnect comprises a spin orbit coupling material; a circuitry to sense values stored in the array, and to provide an output; and a comparator to compare the output with a code.

公开(公告)号：US10326293B2

公开(公告)日：2019-06-18

申请号：US15034990

申请日：2013-12-27

Applicant: INTEL CORPORATION

Inventor： Lilly Huang ,  Wayne Proefrock ,  Krishnan Ravichandran ,  Alexander Uan-Zo-Li

IPC: H02J7/00 ,  H01M10/44 ,  H02J7/35

Abstract: An electronic device may include a battery charger and a controller. The battery charger may receive a voltage from an energy source, and may provide an output power. The controller may receive a voltage value of the energy source, may receive a current value from the battery charger or the energy source, may determine a power value based on the received voltage value and the received current value, and may provide at least one control signal to the battery charger to change the output power of the charger.

公开(公告)号：US20190094931A1

公开(公告)日：2019-03-28

申请号：US15718991

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： Khondker Z. Ahmed ,  Vivek K. De ,  Nachiket V. Desai ,  Suhwan Kim ,  Harish K. Krishnamurthy ,  Xiaosen Liu ,  Turbo Majumder ,  Krishnan Ravichandran ,  Christopher Schaef ,  Vaibhav Vaidya ,  Sriram R. Vangal

IPC: G06F1/26 ,  G06N99/00

Abstract: Various embodiments of the invention may analyze previous patterns of harvested energy to predict future patterns of available harvested energy. This prediction may then be used to choose from among multiple methods of energy reduction techniques. The energy reduction techniques may include multiple versions of reducing or modifying instruction execution. Reduced instruction execution may include reducing the precision of various calculations.

公开(公告)号：US20190006939A1

公开(公告)日：2019-01-03

申请号：US15638643

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： Harish Krishnamurthy ,  Khondker Ahmed ,  Vivek De ,  Nachiket Desai ,  Suhwan Kim ,  Xiaosen Liu ,  Turbo Majumder ,  Krishnan Ravichandran ,  Christopher Schaef ,  Vaibhav Vaidya ,  Sriram Vangal

IPC: H02M1/42 ,  H04W84/20

Abstract: Embodiments described herein describe operating a master-slave controller. Operating the master-slave controller comprises, based on a determination that the first output voltage value is greater than the second output voltage value, calculating a first duty cycle value and an input voltage value and the second voltage regulator, calculating a second duty cycle value based on the first duty cycle value, and based on a determination that the second output voltage value is greater than or equal to the first output voltage value, calculating the second duty cycle value based on the second output voltage value and the input voltage value and calculating the first duty cycle value based on the second duty cycle value and configuring the first voltage regulator with the first duty cycle value and the second voltage regulator with the second duty cycle value.

公开(公告)号：US10122205B2

公开(公告)日：2018-11-06

申请号：US14976210

申请日：2015-12-21

Applicant: INTEL CORPORATION

Inventor： Naoki Matsumura ,  Andrew W. Keates ,  Krishnan Ravichandran

IPC: H02J7/00 ,  H02J7/35

Abstract: A system for increasing the life of a battery cell by limiting the charging of the battery to less than full charge in response to a predicted electricity draw of a connected device being less than the full capacity of the battery before a predicted recharge will occur. The current draw of the connected device may be affected by the amount of time before a next recharge and environmental factors. The system may further comprise one or more sensors to gather data pertaining to environmental conditions that may be used in the calculation of a charge termination value. The charge termination value is an amount of charge to power the device for a duration of time at least until a predicted recharge begins.

公开(公告)号：US09882383B2

公开(公告)日：2018-01-30

申请号：US14581903

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Harish K. Krishnamurthy ,  Khondker Z. Ahmed ,  Krishnan Ravichandran

IPC: H02J3/00 ,  H02J3/14 ,  H02J1/10

CPC classification number: H02J3/00 ,  G06F1/26 ,  G06F1/263 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  H02J1/10

Abstract: Examples may include a smart power delivery network using voltage regulators to supply combined power sufficient to meet a peak load demand generated from one load from among multiple possible loads. A system of power gate devices having controllers may assist in dynamically steering current driven by the voltage regulators to the multiple possible loads.

公开(公告)号：US09798367B2

公开(公告)日：2017-10-24

申请号：US13859704

申请日：2013-04-09

Applicant: Intel Corporation

Inventor： Lilly Huang ,  Wayne L. Proefrock ,  Krishnan Ravichandran ,  Bernd Nordhausen ,  Frank K. Welch, Jr. ,  John G. Tompkins ,  Vaibhav Vaidya

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/28 ,  G06F1/30 ,  H02M3/158 ,  H02J1/14 ,  H02M1/00

CPC classification number: G06F1/26 ,  G06F1/28 ,  G06F1/305 ,  H02J1/14 ,  H02M3/1582 ,  H02M2001/008

Abstract: Methods and apparatus relating to controlling the supply of power to computing devices with dynamically variable energy capacity are described. In one embodiment, logic causes modification to supply of power from a power source to one or more loads in response to a comparison of an output of the power source and a threshold value. The output of the power source may vary over a time period (e.g., oscillating) that causes the one or more loads to become inoperational. Other embodiments are also disclosed and claimed.

公开(公告)号：US09710422B2

公开(公告)日：2017-07-18

申请号：US14570898

申请日：2014-12-15

Applicant: Intel Corporation

Inventor： Sheldon Weng ,  George E. Matthew ,  Pavan Kumar ,  Wayne L. Proefrock ,  Harish K. Krishnamurthy ,  Krishnan Ravichandran

IPC: G06F13/42 ,  G06F13/364 ,  G06F13/40 ,  G06F1/32 ,  G06F1/26

CPC classification number: G06F13/4282 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3253 ,  G06F13/364 ,  G06F13/404 ,  G06F2213/0052 ,  Y02D10/151

Abstract: Methods and apparatus relating to low cost and/or low overhead serial interface for power management and other IC (Integrated Circuit) devices are described. In an embodiment, a unique address is assigned to each of a plurality of slave devices. The plurality of slave devices are coupled in a daisy chain configuration. And, any access directed at a first slave device from the plurality of slave devices is allowed based at least in part on comparison of an address of the first slave device and an address associated with the access. Other embodiments are also disclosed and claimed.

公开(公告)号：US20170187283A1

公开(公告)日：2017-06-29

申请号：US14757732

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Vaibhav Vaidya ,  Vivek K. De ,  Krishnan Ravichandran

IPC: H02M3/158

CPC classification number: H02M3/158 ,  H02M1/083 ,  H02M3/1588 ,  Y02B70/1466

Abstract: Generally, this disclosure describes an apparatus. The apparatus includes switch controller circuitry and zero crossing logic circuitry. The switch controller circuitry is to control a conduction state of a high side switch and a low side switch in a DC to DC converter. The zero crossing logic circuitry includes phase comparator circuitry, a first clocking circuitry and a second clocking circuitry. Each clocking circuitry includes one or more delay elements. The zero crossing logic circuitry is to monitor a switch node voltage, Vsw, and to determine whether Vsw is greater than a reference, Vref. The switch controller circuitry is to turn off a low side switch if Vsw is greater than Vref while the low side switch is turned on, Vsw greater than Vref corresponding to a negative inductor current.