公开(公告)号：US20230195547A1

公开(公告)日：2023-06-22

申请号：US17556682

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Marcos Carranza ,  Cesar Martinez-Spessot ,  Mateo Guzman ,  Francesc Guim Bernat ,  Karthik Kumar ,  Rajesh Poornachandran ,  Kshitij Arun Doshi

IPC: G06F9/54 ,  H04L67/133

CPC classification number: G06F9/547 ,  H04L67/40

Abstract: Embodiments described herein are generally directed to the use of sidecars to perform dynamic API contract generation and conversion. In an example, a first call by a first microservice to a first API of a second microservice is intercepted by a first sidecar of the first microservice. The first API is of a first API type of multiple API types and is specified by a first contract. An API type of the multiple API types is selected by the first sidecar. Responsive to determining the selected API type differs from the first API type, based on the first contract, a second contract is generated by the first sidecar specifying a second API of the selected API type; and a second sidecar of the second microservice is caused to generate the second API and internally connect the second API to the first API based on the second contract.

公开(公告)号：US11662222B2

公开(公告)日：2023-05-30

申请号：US17740599

申请日：2022-05-10

Applicant: Intel Corporation

Inventor： Kshitij Arun Doshi ,  Tao Zhong ,  Gang Yi Deng ,  Zhongyan Lu

IPC: G01D21/00 ,  H04L67/12 ,  G01D3/08 ,  G01D3/10 ,  G16Y20/20 ,  G16Y40/20

CPC classification number: G01D3/08 ,  G01D3/10 ,  G01D21/00 ,  H04L67/12 ,  G16Y20/20 ,  G16Y40/20

Abstract: A system and method for managing sensors including determining health operation states of the sensors correlative with sensor accuracy, classifying the sensors by their respective health operation state, and teaming two sensors each having a health operation state that is intermediate to give a team having a health operation state that is healthy. The sampling frequency of the sensors to determine sensor accuracy may be dynamic.

公开(公告)号：US20220329433A1

公开(公告)日：2022-10-13

申请号：US17842982

申请日：2022-06-17

Applicant: Intel Corporation

Inventor： Kshitij Arun Doshi ,  Christian Maciocco ,  Ned M. Smith ,  Francesc Guim Bernat ,  Satish Jha ,  Vesh Raj Sharma Banjade ,  Arvind Merwaday ,  S M Iftekharul Alam ,  Kuilin Clark Chen

IPC: H04L9/32 ,  H04L9/40

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to protect distributed data. An example apparatus includes at least one memory, machine readable instructions, and processor circuitry to at least one of instantiate or execute the machine readable instructions to detect a key identifier combination from a distributed key, identify a match between the key identifier combination and a platform identifier combination, extract a second key from the distributed key, the second key associated with the object, and decrypt the object via the extracted second key.

公开(公告)号：US11356339B2

公开(公告)日：2022-06-07

申请号：US17066400

申请日：2020-10-08

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Kshitij Arun Doshi ,  Suraj Prabhakaran ,  Raghu Kondapalli ,  Alexander Bachmutsky

IPC: H04L29/08 ,  G06F17/30 ,  G06F11/34 ,  G06F11/30 ,  H04L41/5019 ,  H04L67/12 ,  H04L67/63 ,  H04L67/61 ,  H04L41/0806 ,  H04L41/5041 ,  G06N5/04

Abstract: Various systems and methods for implementing a service-level agreement (SLA) apparatus receive a request from a requester via a network interface of the gateway, the request comprising an inference model identifier that identifies a handler of the request, and a response time indicator. The response time indicator relates to a time within which the request is to be handled indicates an undefined time within which the request is to be handled. The apparatus determines a network location of a handler that is a platform or an inference model to handle the request consistent with the response time indicator, and routes the request to the handler at the network location.

公开(公告)号：US20220012129A1

公开(公告)日：2022-01-13

申请号：US17484951

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Kshitij Arun Doshi ,  Francesc Guim Bernat ,  Christian Maciocco ,  Satish Jha ,  Vesh Raj Sharma Banjade ,  S M Iftekharul Alam ,  Alexander Bachmutsky

IPC: G06F11/14 ,  G06F11/07

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to increase resiliency in self-healing mechanisms. At least one non-transitory machine-readable medium comprises instructions that, when executed, cause at least one processor to at least partition computational resources of a first host into a primary partition and a shadow partition, the primary partition to communicate with a second host, apply a fix for the primary partition, determine if the primary partition can communicate with the second host during the application of the fix, cause, in response to the determination that the primary partition cannot communicate with the second host during the application of the fix, the shadow partition to communicate with the second host; and transfer communication with the second host from the shadow partition to the primary partition, the transfer in response to a determination that the application of the fix is complete.

公开(公告)号：US11212124B2

公开(公告)日：2021-12-28

申请号：US16235894

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Dario Sabella ,  Ned M. Smith ,  Neal Oliver ,  Kshitij Arun Doshi ,  Suraj Prabhakaran ,  Miltiadis Filippou ,  Francesc Guim Bernat

IPC: H04L12/14 ,  H04L29/08 ,  H04M15/00 ,  H04W4/24

Abstract: An architecture to allow Multi-Access Edge Computing (MEC) billing and charge tracking, is disclosed. In an example, a tracking process, such as is performed by an edge computing apparatus, includes: receiving a computational processing request for a service operated with computing resources of the edge computing apparatus from a connected edge device within the first access network, wherein the computational processing request includes an identification of the connected edge device; identifying a processing device, within the first access network, for performing the computational processing request; and storing the identification of the connected edge device, a processing device identification, and data describing the computational processes completed by the processing device in association with the computational processing request.

公开(公告)号：US11139991B2

公开(公告)日：2021-10-05

申请号：US16722917

申请日：2019-12-20

Applicant: Intel Corporation

Inventor： Kshitij Arun Doshi ,  Ned M. Smith ,  Francesc Guim Bernat ,  Kevin B. Stanton

IPC: H04L29/06 ,  H04L9/32 ,  G06F12/14 ,  H04L9/08 ,  G06F9/455 ,  G06F16/18 ,  G06F16/23 ,  G06F11/10 ,  H04L9/06 ,  H04L12/24 ,  H04L12/26 ,  H04L29/08 ,  G06F9/54 ,  G06F21/60 ,  H04L9/00 ,  H04L12/911 ,  G06F8/41 ,  G06F9/38 ,  G06F9/445 ,  G06F9/48 ,  G06F9/50 ,  G06F11/34 ,  G16Y40/10

Abstract: Various approaches for coordinating edge computing transactions are described, based on the generation and verification of fine-grained timestamp values among distributed computing entities in an edge computing system. In an edge computing system, an edge computing device performs operations to obtain transaction data, a timestamp, and a timestamp signature for a transaction, with the timestamp generated from a secure (and attestable) timestamp procedure that is coordinated with another entity (including via a network-coordinated timestamp synchronization). This timestamp is verified by the device based on the timestamp signature and the transaction data for the transaction, and the transaction is conducted (e.g., using a value of the timestamp) at the device or elsewhere in the system based on successful verification. In further examples, the coordinated timestamp enables multi-version concurrency control (MVCC) database transactions, verification of blockchain transactions, or other uses and verifications of timestamp values.

公开(公告)号：US20210099362A1

公开(公告)日：2021-04-01

申请号：US17066400

申请日：2020-10-08

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Kshitij Arun Doshi ,  Suraj Prabhakaran ,  Raghu Kondapalli ,  Alexander Bachmutsky

IPC: H04L12/24 ,  H04L29/08

Abstract: Various systems and methods for implementing a service-level agreement (SLA) apparatus receive a request from a requester via a network interface of the gateway, the request comprising an inference model identifier that identifies a handler of the request, and a response time indicator. The response time indicator relates to a time within which the request is to be handled indicates an undefined time within which the request is to be handled. The apparatus determines a network location of a handler that is a platform or an inference model to handle the request consistent with the response time indicator, and routes the request to the handler at the network location.

公开(公告)号：US12206552B2

公开(公告)日：2025-01-21

申请号：US17119785

申请日：2020-12-11

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Kshitij Arun Doshi ,  Kapil Sood ,  Tarun Viswanathan

IPC: H04L29/06 ,  G06F1/20 ,  G06F9/48 ,  G06F9/50 ,  G06F9/54 ,  G06F11/30 ,  H04L9/06 ,  H04L9/32 ,  H04L41/084 ,  H04L41/0869 ,  H04L41/5054 ,  H04L47/78 ,  H04L49/00 ,  H04L67/10 ,  H04W4/08 ,  H04W12/04

Abstract: Various aspects of methods, systems, and use cases for multi-entity (e.g., multi-tenant) edge computing deployments are disclosed. Among other examples, various configurations and features enable the management of resources (e.g., controlling and orchestrating hardware, acceleration, network, processing resource usage), security (e.g., secure execution and communication, isolation, conflicts), and service management (e.g., orchestration, connectivity, workload coordination), in edge computing deployments, such as by a plurality of edge nodes of an edge computing environment configured for executing workloads from among multiple tenants.

公开(公告)号：US12177277B2

公开(公告)日：2024-12-24

申请号：US17313353

申请日：2021-05-06

Applicant: Intel Corporation

Inventor： Lokpraveen Mosur ,  Ilango Ganga ,  Robert Cone ,  Kshitij Arun Doshi ,  John J. Browne ,  Mark Debbage ,  Stephen Doyle ,  Patrick Fleming ,  Doddaballapur Jayasimha

IPC: H04L65/61 ,  H04L47/50 ,  H04L49/9005

Abstract: In one embodiment, a system includes a device and a host. The device includes a device stream buffer. The host includes a processor to execute at least a first application and a second application, a host stream buffer, and a host scheduler. The first application is associated with a first transmit streaming channel to stream first data from the first application to the device stream buffer. The first transmit streaming channel has a first allocated amount of buffer space in the device stream buffer. The host scheduler schedules enqueue of the first data from the first application to the first transmit streaming channel based at least in part on availability of space in the first allocated amount of buffer space in the device stream buffer. Other embodiments are described and claimed.