公开(公告)号：US20220310601A1

公开(公告)日：2022-09-29

申请号：US17211745

申请日：2021-03-24

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Cory WEBER ,  Stephen M. CEA ,  Leonard C. PIPES ,  Seahee HWANGBO ,  Rishabh MEHANDRU ,  Patrick KEYS ,  Jack YAUNG ,  Tzu-Min OU

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: Fin doping, and integrated circuit structures resulting therefrom, are described. In an example, an integrated circuit structure includes a semiconductor fin. A lower portion of the semiconductor fin includes a region having both N-type dopants and P-type dopants with a net excess of the P-type dopants of at least 2E18 atoms/cm3. A gate stack is over and conformal with an upper portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack, and a second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

公开(公告)号：US20220093647A1

公开(公告)日：2022-03-24

申请号：US17030226

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Seung Hoon SUNG ,  Cheng-Ying HUANG ,  Marko RADOSAVLJEVIC ,  Christopher M. NEUMANN ,  Susmita GHOSE ,  Varun MISHRA ,  Cory WEBER ,  Stephen M. CEA ,  Tahir GHANI ,  Jack T. KAVALIEROS

IPC: H01L27/12 ,  H01L21/84

Abstract: Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.

公开(公告)号：US20210233908A1

公开(公告)日：2021-07-29

申请号：US17232010

申请日：2021-04-15

Applicant: Intel Corporation

Inventor： Mark T. BOHR ,  Stephen M. CEA ,  Barbara A. CHAPPELL

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L21/84

Abstract: Through gate fin isolation for non-planar transistors in a microelectronic device, such as an integrated circuit (IC). In embodiments, ends of adjacent semiconductor fins are electrically isolated from each other with an isolation region that is self-aligned to gate electrodes of the semiconductor fins enabling higher transistor packing density and other benefits. In an embodiment, a single mask is employed to form a plurality of sacrificial placeholder stripes of a fixed pitch, a first subset of placeholder stripes is removed and isolation cuts made into the semiconductor fins in openings resulting from the first subset removal while a second subset of the placeholder stripes is replaced with gate electrodes.

公开(公告)号：US20200227520A1

公开(公告)日：2020-07-16

申请号：US16831692

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Kelin J. KUHN ,  Seiyon KIM ,  Rafael RIOS ,  Stephen M. CEA ,  Martin D. GILES ,  Annalisa CAPPELLANI ,  Titash RAKSHIT ,  Peter CHANG ,  Willy RACHMADY

IPC: H01L29/06 ,  B82Y10/00 ,  H01L21/762 ,  H01L29/16 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L29/165 ,  H01L27/092 ,  H01L27/12 ,  H01L29/10

Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

公开(公告)号：US20200176482A1

公开(公告)日：2020-06-04

申请号：US16785986

申请日：2020-02-10

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Patrick MORROW ,  Stephen M. CEA ,  Rishabh MEHANDRU ,  Cory E. WEBER

IPC: H01L27/12 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/3115 ,  H01L21/84

Abstract: Embodiments of the present invention are directed to formation of fins with different active channel heights in a tri-gate or a Fin-FET device. In an embodiment, at least two fins are formed on a front side of the substrate. A gate structure extends over a top surface and a pair of sidewalls of at least a portion of the fins. In an embodiment, the substrate is thinned to expose the bottom surface of the fins. Next, backside etching may be performed on each fin to form active channel regions. The fins may be recessed to different depths, forming active channel regions with differing heights.

公开(公告)号：US20200152797A1

公开(公告)日：2020-05-14

申请号：US16740089

申请日：2020-01-10

Applicant: Intel Corporation

Inventor： Stephen M. CEA ,  Annalisa CAPPELLANI ,  Martin D. GILES ,  Rafael RIOS ,  Seiyon KIM ,  Kelin J. KUHN

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423 ,  H01L29/06 ,  H01L21/268 ,  H01L29/78

Abstract: Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.

公开(公告)号：US20200035818A1

公开(公告)日：2020-01-30

申请号：US16592380

申请日：2019-10-03

Applicant: Intel Corporation

Inventor： Stephen M. CEA ,  Cory E. WEBER ,  Patrick H. KEYS ,  Seiyon KIM ,  Michael G. HAVERTY ,  Sadasivan SHANKAR

IPC: H01L29/775 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/66 ,  H01L29/417 ,  H01L29/786 ,  H01L29/78

Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.

公开(公告)号：US20170317172A1

公开(公告)日：2017-11-02

申请号：US15650569

申请日：2017-07-14

Applicant: Intel Corporation

Inventor： Jack T. KAVALIEROS ,  Nancy ZELICK ,  Been-Yih JIN ,  Markus KUHN ,  Stephen M. CEA

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/161 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854

Abstract: Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.