公开(公告)号：US20240088254A1

公开(公告)日：2024-03-14

申请号：US18514995

申请日：2023-11-20

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Rishabh MEHANDRU ,  Cory WEBER ,  Willy RACHMADY ,  Varun MISHRA

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/0217 ,  H01L21/02293 ,  H01L21/02532 ,  H01L21/823431 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1091 ,  H01L29/165 ,  H01L29/42368 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

Abstract: Gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, are described. For example, an integrated circuit structure includes an insulator fin on an insulator substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack is overlying the insulator fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and at first and second ends of the insulator fin.

公开(公告)号：US20230317786A1

公开(公告)日：2023-10-05

申请号：US17700215

申请日：2022-03-21

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Cory WEBER ,  Varun MISHRA ,  Tahir GHANI ,  Pratik PATEL ,  Wonil CHUNG ,  Mohammad HASAN

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/0673 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439

Abstract: Gate-all-around integrated circuit structures having necked features, and methods of fabricating gate-all-around integrated circuit structures having necked features, are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires. Each nanowire of the vertical stack of horizontal nanowires has a channel portion with a first vertical thickness and has end portions with a second vertical thickness greater than the first vertical thickness. A gate stack is surrounding the channel portion of each nanowire of the vertical stack of horizontal nanowires.

公开(公告)号：US20220238685A1

公开(公告)日：2022-07-28

申请号：US17724331

申请日：2022-04-19

Applicant: Intel Corporation

Inventor： Abhishek SHARMA ,  Cory WEBER ,  Van H. LE ,  Sean MA

IPC: H01L29/47 ,  H01L27/108 ,  H01L27/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a gate electrode above the substrate, and a channel layer above the substrate, separated from the gate electrode by a gate dielectric layer. The transistor further includes a contact electrode above the channel layer and in contact with a contact area of the channel layer. The contact area has a thickness determined based on a Schottky barrier height of a Schottky barrier formed at an interface between the contact electrode and the contact area, a doping concentration of the contact area, and a contact resistance at the interface between the contact electrode and the contact area. Other embodiments may be described and/or claimed.

公开(公告)号：US20240006483A1

公开(公告)日：2024-01-04

申请号：US17855567

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Rishabh MEHANDRU ,  Anand S. MURTHY ,  Wilfred GOMES ,  Cory WEBER ,  Sagar SUTHRAM

IPC: H01L29/06 ,  H01L29/786 ,  H01L27/088 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L29/78618 ,  H01L29/78696 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/7851

Abstract: Structures having raised epitaxy on channel structure transistors are described. In an example, an integrated circuit structure includes a channel structure having multi-layer epitaxial source or drain structures thereon, the multi-layer epitaxial source or drain structures having a recess extending there through. A gate dielectric layer is on a bottom and along sides of the recess and laterally surrounded by the epitaxial source or drain structures. A gate electrode is on and laterally surrounded by the gate dielectric layer. The gate electrode has an uppermost surface below an uppermost surface of the gate dielectric layer.

公开(公告)号：US20220310601A1

公开(公告)日：2022-09-29

申请号：US17211745

申请日：2021-03-24

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Cory WEBER ,  Stephen M. CEA ,  Leonard C. PIPES ,  Seahee HWANGBO ,  Rishabh MEHANDRU ,  Patrick KEYS ,  Jack YAUNG ,  Tzu-Min OU

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: Fin doping, and integrated circuit structures resulting therefrom, are described. In an example, an integrated circuit structure includes a semiconductor fin. A lower portion of the semiconductor fin includes a region having both N-type dopants and P-type dopants with a net excess of the P-type dopants of at least 2E18 atoms/cm3. A gate stack is over and conformal with an upper portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack, and a second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

公开(公告)号：US20220093647A1

公开(公告)日：2022-03-24

申请号：US17030226

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Seung Hoon SUNG ,  Cheng-Ying HUANG ,  Marko RADOSAVLJEVIC ,  Christopher M. NEUMANN ,  Susmita GHOSE ,  Varun MISHRA ,  Cory WEBER ,  Stephen M. CEA ,  Tahir GHANI ,  Jack T. KAVALIEROS

IPC: H01L27/12 ,  H01L21/84

Abstract: Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.

公开(公告)号：US20240006416A1

公开(公告)日：2024-01-04

申请号：US17855598

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Anand S. MURTHY ,  Sagar SUTHRAM ,  Pushkar RANADE ,  Wilfred GOMES ,  Rishabh MEHANDRU ,  Cory WEBER

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: Structures having ultra-high conductivity global routing are described. In an example, an integrated circuit structure includes a device layer having a plurality of transistors. A plurality of metallization layers is above the plurality of transistors of the device layer. One or more of the metal layers includes a material having a critical temperature greater than 10 Kelvin and less than 300 Kelvin.

公开(公告)号：US20240006412A1

公开(公告)日：2024-01-04

申请号：US17855608

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Anand S. MURTHY ,  Rishabh MEHANDRU ,  Cory WEBER ,  Sagar SUTHRAM ,  Pushkar RANADE ,  Wilfred GOMES

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0886 ,  H01L29/0673 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: Structures having recessed channel transistors are described. In an example, an integrated circuit structure includes a channel structure having a recess extending partially there through. A gate dielectric layer is on a bottom and along sides of the recess, the gate dielectric layer laterally surrounded by the channel structure. A gate electrode is on and laterally surrounded by the gate dielectric layer. The gate electrode has an uppermost surface below and uppermost surface of the channel structure.

公开(公告)号：US20230422485A1

公开(公告)日：2023-12-28

申请号：US17851967

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Sagar SUTHRAM ,  Wilfred GOMES ,  Tahir GHANI ,  Rishabh MEHANDRU ,  Cory WEBER ,  Anand S. MURTHY

IPC: H01L27/108 ,  H01L29/06 ,  H01L23/522 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/10841 ,  H01L29/0673 ,  H01L23/5226 ,  H01L29/42392 ,  H01L29/78696

Abstract: Structures having memory with backside DRAM and power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based transistors of the device layer. A backside structure is below the nanowire-based transistors of the device layer. The backside structure includes a plurality of dynamic random access memory (DRAM) devices.

公开(公告)号：US20200098880A1

公开(公告)日：2020-03-26

申请号：US16142045

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Abhishek SHARMA ,  Cory WEBER ,  Van H. LE ,  Sean MA

IPC: H01L29/47 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L27/108 ,  H01L27/24

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a gate electrode above the substrate, and a channel layer above the substrate, separated from the gate electrode by a gate dielectric layer. The transistor further includes a contact electrode above the channel layer and in contact with a contact area of the channel layer. The contact area has a thickness determined based on a Schottky barrier height of a Schottky barrier formed at an interface between the contact electrode and the contact area, a doping concentration of the contact area, and a contact resistance at the interface between the contact electrode and the contact area. Other embodiments may be described and/or claimed.