公开(公告)号：US10698689B2

公开(公告)日：2020-06-30

申请号：US16120226

申请日：2018-09-01

Applicant: Intel Corporation

Inventor： Pratik J. Ashar ,  Supratim Pal ,  Subramaniam Maiyuran ,  Wei-Yu Chen ,  Guei-Yuan Lueh

IPC: G06F8/41 ,  G06F9/38 ,  G06F9/30 ,  G06F9/50

Abstract: An apparatus to facilitate register sharing is disclosed. The apparatus includes one or more processors to generate first machine code having a first General Purpose Register (GRF) per thread ratio, detect an occurrence of one or more spill/fill instructions in the first machine code, and generate second machine code having a second GRF per thread ratio upon a detection of one or more spill/fill instructions in the first machine code, wherein the second GRF per thread ratio is based on a disabling of a first of a plurality of hardware threads.

公开(公告)号：US10599571B2

公开(公告)日：2020-03-24

申请号：US15670265

申请日：2017-08-07

Applicant: Intel Corporation

Inventor： Vasileios Porpodas ,  Guei-Yuan Lueh ,  Subramaniam Maiyuran ,  Wei-Yu Chen

IPC: G06F9/30 ,  G06F12/0862 ,  G06F12/0875 ,  G06F8/41

Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a cache, one or more execution units (EUs) to execute program code, prefetch logic to maintain tracking information of memory instructions in the program code that trigger a cache miss and compiler logic to receive the tracking information, insert one or more pre-fetch instructions in updated program code to prefetch data from a memory for execution of one or more of the memory instructions that triggered a cache miss and download the updated program code for execution by the one or more EUs.

公开(公告)号：US10282227B2

公开(公告)日：2019-05-07

申请号：US14543982

申请日：2014-11-18

Applicant: Intel Corporation

Inventor： Guei-Yuan Lueh ,  Subramaniam Maiyuran ,  Wei-Yu Chen ,  Kaiyu Chen

IPC: G06F9/46

Abstract: Systems and methods may provide for inserting one or more preemption instructions while compiling a computer program. The one or more preemption instructions being inserted within a preemption window in the computer program reduces the number of live registers at each preemption instruction position. Further, the preemption instruction instructs which registers are to be saved at a particular program position, typically the registers that are live at that program position. The compiled program may be run in an execution unit. A preemption request may be made to the execution unit and executed at a next available preemption instruction in the program being run in the execution unit.

公开(公告)号：US20190042433A1

公开(公告)日：2019-02-07

申请号：US15670265

申请日：2017-08-07

Applicant: Intel Corporation

Inventor： Vasileios Porpodas ,  Guei-Yuan Lueh ,  Subramaniam Maiyuran ,  Wei-Yu Chen

IPC: G06F12/0862 ,  G06F12/0875 ,  G06F9/30

Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a cache, one or more execution units (EUs) to execute program code, prefetch logic to maintain tracking information of memory instructions in the program code that trigger a cache miss and compiler logic to receive the tracking information, insert one or more pre-fetch instructions in updated program code to prefetch data from a memory for execution of one or more of the memory instructions that triggered a cache miss and download the updated program code for execution by the one or more EUs.

公开(公告)号：US20170177369A1

公开(公告)日：2017-06-22

申请号：US14976788

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Peng Guo ,  Wei-Yu Chen ,  Guei-Yuan Lueh ,  Subramaniam Maiyuran

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/3016 ,  G06F9/30181 ,  G06F9/345

Abstract: Methods and apparatus relating to non-contiguous multiple register access for microprocessor data exchange instructions are described. In an embodiment, a plurality of registers store data. A processor exchanges the stored data between the one or more of the plurality of registers and a logic component in response to a single instruction. The plurality of registers are non-contiguous. Other embodiments are also disclosed and claimed.

公开(公告)号：US12164430B2

公开(公告)日：2024-12-10

申请号：US18470553

申请日：2023-09-20

Applicant: Intel Corporation

Inventor： Vasileios Porpodas ,  Guei-Yuan Lueh ,  Subramaniam Maiyuran ,  Wei-Yu Chen

IPC: G06F12/0862 ,  G06F8/41 ,  G06F9/30 ,  G06F12/0875

Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a cache, one or more execution units (EUs) to execute program code, prefetch logic to maintain tracking information of memory instructions in the program code that trigger a cache miss and compiler logic to receive the tracking information, insert one or more pre-fetch instructions in updated program code to prefetch data from a memory for execution of one or more of the memory instructions that triggered a cache miss and download the updated program code for execution by the one or more EUs.

公开(公告)号：US11314515B2

公开(公告)日：2022-04-26

申请号：US16724831

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Supratim Pal ,  Sasikanth Avancha ,  Ishwar Bhati ,  Wei-Yu Chen ,  Dipankar Das ,  Ashutosh Garg ,  Chandra S. Gurram ,  Junjie Gu ,  Guei-Yuan Lueh ,  Subramaniam Maiyuran ,  Jorge E. Parra ,  Sudarshan Srinivasan ,  Varghese George

IPC: G06F9/38 ,  G06F9/30

Abstract: Embodiments described herein provide for an instruction and associated logic to enable a vector multiply add instructions with automatic zero skipping for sparse input. One embodiment provides for a general-purpose graphics processor comprising logic to perform operations comprising fetching a hardware macro instruction having a predicate mask, a repeat count, and a set of initial operands, where the initial operands include a destination operand and multiple source operands. The hardware macro instruction is configured to perform one or more multiply/add operations on input data associated with a set of matrices.

公开(公告)号：US20210125581A1

公开(公告)日：2021-04-29

申请号：US17062871

申请日：2020-10-05

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Guei-Yuan Lueh ,  James A. Valerio ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Vasanth Ranganathan ,  Kalyan K. Bhiravabhatla ,  Arthur D. Hunter, JR. ,  Wei-Yu Chen ,  Subramaniam M. Maiyuran

IPC: G09G5/36 ,  G06F12/0875 ,  G06F9/46 ,  G09G5/00

Abstract: A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.

公开(公告)号：US20200174933A1

公开(公告)日：2020-06-04

申请号：US16787841

申请日：2020-02-11

Applicant: Intel Corporation

Inventor： Vasileios Porpodas ,  Guei-Yuan Lueh ,  Subramaniam Maiyuran ,  Wei-Yu Chen

IPC: G06F12/0862 ,  G06F9/30 ,  G06F12/0875 ,  G06F8/41

Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a cache, one or more execution units (EUs) to execute program code, prefetch logic to maintain tracking information of memory instructions in the program code that trigger a cache miss and compiler logic to receive the tracking information, insert one or more pre-fetch instructions in updated program code to prefetch data from a memory for execution of one or more of the memory instructions that triggered a cache miss and download the updated program code for execution by the one or more EUs.

公开(公告)号：US10453427B2

公开(公告)日：2019-10-22

申请号：US15477030

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Guei-Yuan Lueh ,  James A. Valerio ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Vasanth Ranganathan ,  Kalyan Bhairavabhatla ,  Arthur D. Hunter, Jr. ,  Wei-Yu Chen ,  Subramaniam M. Maiyuran

IPC: G09G5/36 ,  G06F9/46 ,  G06F12/0875 ,  G09G5/00 ,  G06F12/084 ,  G06F12/0811

Abstract: A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.