公开(公告)号：US20060160379A1

公开(公告)日：2006-07-20

申请号：US11369781

申请日：2006-03-07

Applicant: James Rathburn

Inventor： James Rathburn

IPC: H01R12/00

CPC classification number: H01R13/2414 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/48 ,  H01L2224/16227 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/81191 ,  H01L2224/81898 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01R12/52 ,  H01R12/61 ,  H01R12/62 ,  H01R12/7082 ,  H01R12/714 ,  H01R12/79 ,  H01R13/2442 ,  H05K3/326 ,  H05K3/365 ,  Y10T29/49128 ,  Y10T29/49139 ,  Y10T29/49151 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/0401

Abstract: An apparatus and method for making a compliant interconnect assembly adapted to electrically couple a first circuit member to a second circuit member. The first dielectric layer has a first major surface and a plurality of through openings. A plurality of electrical traces are positioned against the first major surface of the first dielectric layer. The electric traces include a plurality of conductive compliant members having first distal ends aligned with a plurality of the openings in the first dielectric layer. The first distal ends are adapted to electrically couple with the first circuit member. The second dielectric layer has a first major surface positioned against the electric traces and the first major surface of the first dielectric layer. The second dielectric layer has a plurality of through openings through which the electric traces electrically couple with the second circuit member.

公开(公告)号：US20060035483A1

公开(公告)日：2006-02-16

申请号：US11253510

申请日：2005-10-19

Applicant: James Rathburn ,  Martin Cavegn

Inventor： James Rathburn ,  Martin Cavegn

IPC: H01R12/00

CPC classification number: H01R13/112 ,  H01R12/52 ,  H01R12/57 ,  H01R12/7082 ,  H01R13/24 ,  H01R13/2414 ,  H01R13/2435 ,  H05K3/3426

Abstract: An electrical interconnect assembly for electrically interconnecting terminals on a first circuit member with terminals on a second circuit member. The electrical interconnect assembly includes a housing having a plurality of through openings extending between a first surface and a second surface. A plurality of contact members are positioned in a plurality of the through openings. The contact members include a base portion, a first beam having a proximal end attached to the base portion and a distal end extending away from the base portion in a first direction, and a second beam having a proximal end attached to the base portion and a distal end extending away from the base portion generally in the first direction. The first and second beams are configured to form at least one loop. At least one tab is attached to the base portion. The tab includes at least one engagement feature mechanically coupled to a solder member.

Abstract translation: 一种电互连组件，用于将第一电路构件上的端子与第二电路构件上的端子电连接。 电互连组件包括具有在第一表面和第二表面之间延伸的多个通孔的壳体。 多个接触构件定位在多个通孔中。 接触构件包括基部，具有附接到基部的近端的第一梁和在第一方向上远离基部延伸的远端，以及具有附接到基部的近端的第二梁和 远端基本上沿第一方向远离基部。 第一和第二梁被配置成形成至少一个环。 至少一个突片附接到基部。 该突片包括机械地联接到焊料构件的至少一个接合特征。

公开(公告)号：US20050221675A1

公开(公告)日：2005-10-06

申请号：US11030213

申请日：2005-01-04

Applicant: James Rathburn ,  Martin Cavegn

Inventor： James Rathburn ,  Martin Cavegn

IPC: H01R12/16 ,  H01R13/24 ,  H01R24/00

CPC classification number: H01R13/2414 ,  H01R12/523 ,  H01R13/2435

Abstract: An electrical interconnect assembly for electrically interconnecting terminals on a first circuit member with terminals on a second circuit member. The electrical interconnect assembly includes a housing having a plurality of through openings extending between a first surface and a second surface. A plurality of electrical contact member are positioned in a plurality of the through openings. The contact members have at least one engagement feature forming a snap-fit relationship with the housing. A stabilizing structure on the housing limits deflection of the contact members in at least one direction.

Abstract translation: 一种电互连组件，用于将第一电路构件上的端子与第二电路构件上的端子电连接。 电互连组件包括具有在第一表面和第二表面之间延伸的多个通孔的壳体。 多个电接触构件定位在多个通孔中。 接触构件具有与壳体形成卡扣配合关系的至少一个接合特征。 壳体上的稳定结构限制了接触构件在至少一个方向上的挠曲。

公开(公告)号：US09613841B2

公开(公告)日：2017-04-04

申请号：US13410943

申请日：2012-03-02

Applicant: James Rathburn

Inventor： James Rathburn

IPC: H01L23/48 ,  H01L21/60 ,  H01L21/683 ,  H01L23/498 ,  H01L23/60 ,  H01L23/00 ,  H05K3/34

CPC classification number: H01L21/6835 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/60 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81201 ,  H01L2224/8138 ,  H01L2224/819 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K3/3436 ,  H01L2924/00

Abstract: An area array integrated circuit (IC) package for an IC device. The IC package includes a first substrate with conductive traces electrically coupled to the IC device. An interconnect assembly having a first surface is mechanically coupled to the first substrate. The interconnect assembly includes a plurality of contact members electrically coupled to the conductive traces on the first substrate. A second substrate is mechanically coupled to a second surface of the interconnect assembly so that the first substrate, the interconnect assembly, and the second substrate substantially surround the IC device. The second substrate includes conductive traces that are electrically coupled to the contact members in the interconnect assembly.

公开(公告)号：US09231328B2

公开(公告)日：2016-01-05

申请号：US13318382

申请日：2010-05-27

Applicant: James Rathburn

Inventor： James Rathburn

IPC: H05K1/11 ,  H05K1/00 ,  H05K7/00 ,  H01R4/58 ,  H01R12/00 ,  H01R13/24

CPC classification number: H01R13/2414 ,  H01R13/2485 ,  Y10T29/49139

Abstract: An interconnect assembly including a resilient material with a plurality of through holes extending from a first surface to a second surface. A plurality of discrete, free-flowing conductive particles is located in the through holes. The conductive particles are preferably substantially free of non-conductive materials. A plurality of first contact tips are located in the through holes adjacent the first surface and a plurality of second contact tips are located in the through holes adjacent the second surface. The resilient material provides the required resilience, while the conductive particles provide a conductive path substantially free of non-conductive materials.

Abstract translation: 一种互连组件，包括具有从第一表面延伸到第二表面的多个通孔的弹性材料。 多个离散的，自由流动的导电颗粒位于通孔中。 导电颗粒优选基本上不含非导电材料。 多个第一接触尖端位于邻近第一表面的通孔中，并且多个第二接触末端位于与第二表面相邻的通孔中。 弹性材料提供所需的弹性，而导电颗粒提供基本上不含非导电材料的导电路径。

公开(公告)号：US09184527B2

公开(公告)日：2015-11-10

申请号：US13700639

申请日：2011-06-02

Applicant: James Rathburn

Inventor： James Rathburn

IPC: H01R13/24 ,  H01R12/70 ,  H05K7/10 ,  H01R13/66 ,  H01R43/20 ,  H01R12/52 ,  H05K3/36

CPC classification number: H01R13/24 ,  H01R12/52 ,  H01R12/7082 ,  H01R13/2421 ,  H01R13/66 ,  H01R43/20 ,  H05K3/361 ,  H05K3/368 ,  H05K7/1069 ,  H05K2201/0187 ,  H05K2201/10378 ,  Y10T29/4922

Abstract: A socket housing and method of making the socket housing. A plurality of dielectric layers are printed with a plurality of recesses on a substrate. The dielectric layers include at least two different dielectric materials. A sacrificial material is printed in the recesses. The assembly is removed from the substrate and the sacrificial material is removed from the recesses. At least one contact member is located in a plurality of the recesses. Distal ends of the contact members are adapted to electrically couple with circuit members.

Abstract translation: 插座壳体和制造插座壳体的方法。 多个电介质层在衬底上印有多个凹槽。 电介质层包括至少两种不同的介电材料。 牺牲材料印在凹槽中。 将组件从衬底移除，并且牺牲材料从凹部移除。 至少一个接触构件位于多个凹部中。 接触构件的远端适于与电路构件电耦合。

公开(公告)号：US08970031B2

公开(公告)日：2015-03-03

申请号：US13319145

申请日：2010-06-15

Applicant: James Rathburn

Inventor： James Rathburn

IPC: H01L23/48 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/6836 ,  H01L23/3107 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/11002 ,  H01L2224/1147 ,  H01L2224/11505 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method of making semiconductor die terminals and a semiconductor device with die terminals made according to the present method. At least a first mask layer is selectively printed on at least a portion of a wafer containing a plurality of the semiconductor devices to create first recesses aligned with electrical terminals on the semiconductor devices. A conductive material is deposited in a plurality of the first recesses to form die terminals on the semiconductor devices. The first mask layer is removed to expose the die terminals, and the wafer is diced into a plurality of discrete semiconductor devices.

Abstract translation: 根据本方法制造半导体管芯端子的方法和具有管芯端子的半导体器件。 至少第一掩模层被选择性地印刷在包含多个半导体器件的晶片的至少一部分上，以形成与半导体器件上的电端子对准的第一凹部。 导电材料沉积在多个第一凹槽中以在半导体器件上形成晶片端子。 去除第一掩模层以露出裸片端子，并将晶片切割成多个分立半导体器件。

公开(公告)号：US08955215B2

公开(公告)日：2015-02-17

申请号：US13266486

申请日：2010-05-25

Applicant: James Rathburn

Inventor： James Rathburn

IPC: H05K3/34 ,  H05K3/30 ,  H01K3/10 ,  H05K1/00 ,  H01R12/57 ,  H01R12/70

CPC classification number: H01R12/7082 ,  H01R12/57 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49165

Abstract: A method of forming an interconnect assembly including forming a substrate with a plurality of through holes extending from a first major surface to a second major surface. A plurality of recesses are formed in the second major surface of the substrate that at least partially overlap with the plurality of through holes. The recesses have a cross-sectional area greater than a cross-sectional area of the through holes. At least one discrete contact member is inserted in a plurality of the through holes. The contact members include proximal ends extending into the recesses, distal ends extending above the first major surface, and intermediate portions engaged with an engagement region of the substrate located between the first major surface and the recesses. Retention members at least partially deposited in the recesses bond to the proximal ends to retain the contact members in the through holes.

Abstract translation: 一种形成互连组件的方法，包括通过从第一主表面延伸到第二主表面的多个通孔形成衬底。 在基板的第二主表面上形成有多个凹部，其与多个通孔至少部分重叠。 凹部的横截面积大于通孔的横截面面积。 至少一个分立的接触构件被插入到多个通孔中。 接触构件包括延伸到凹部中的近端，在第一主表面上方延伸的远端，以及与位于第一主表面和凹部之间的基底的接合区域接合的中间部分。 至少部分地沉积在凹部中的保持构件结合到近端以将接触构件保持在通孔中。

公开(公告)号：US08928344B2

公开(公告)日：2015-01-06

申请号：US13266907

申请日：2010-05-27

Applicant: James Rathburn

Inventor： James Rathburn

IPC: G01R31/00 ,  G01R31/28 ,  G01R31/02

CPC classification number: G01R31/2889 ,  G01R31/024 ,  Y10T29/49004

Abstract: Diagnostic tools for testing integrated circuit (IC) devices, and a method of making the same. The first diagnostic tool includes a first compliant printed circuit with a plurality of contact pads configured to form an electrical interconnect at a first interface between proximal ends of contact members in the socket and contact pads on a printed circuit board (PCB). A plurality of printed conductive traces electrically couple to a plurality of the contact pads on the first compliant printed circuit. A plurality of electrical devices are printed on the first compliant printed circuit at a location external to the first interface. The electrical devices are electrically coupled to the conductive traces and programmed to provide one or more of continuity testing at the first interface or functionality of the IC devices. A second diagnostic tool includes a second compliant printed circuit electrically coupled to a surrogate IC device.

Abstract translation: 用于测试集成电路（IC）器件的诊断工具及其制作方法。 第一诊断工具包括具有多个接触焊盘的第一顺应印刷电路，其被配置为在插座中的接触构件的近端和印刷电路板（PCB）上的接触焊盘之间的第一界面处形成电互连。 多个印刷导电迹线电耦合到第一顺应印刷电路上的多个接触焊盘。 多个电气设备被印刷在第一接合印刷电路上的位于第一接口外部的位置处。 电气设备电耦合到导电迹线并被编程为在IC器件的第一接口或功能性处提供一个或多个连续性测试。 第二诊断工具包括电耦合到替代IC器件的第二顺应印刷电路。

公开(公告)号：US08803539B2

公开(公告)日：2014-08-12

申请号：US13266522

申请日：2010-05-25

Applicant: James Rathburn

Inventor： James Rathburn

IPC: G01R1/067

CPC classification number: G01R1/07314

Abstract: A probe assembly that acts as a temporary interconnect between terminals on a circuit member and a test station. The probe assembly can include a base layer of a dielectric material printed onto a surface of a fixture. The surface of the fixture can have a plurality of cavities. A plurality of discrete contact members can be formed in the plurality of cavities in the fixture and coupled to the base layer. A plurality of conductive traces can be printed onto an exposed surface of the base layer and electrically coupled with proximal ends of one or more of the discrete contact members. A compliant layer can be deposited over the conductive traces and the proximal ends of the contact members. A protective layer can be deposited on the compliant layer such that when the probe assembly is removed from the fixture the distal ends of the contact members contact terminals on the circuit member and the conductive traces electrically couple the circuit member to a test station. Electrical devices on the probe assembly can communicate with the test station to provide adaptive testing.

Abstract translation: 探针组件，用作电路元件端子和测试台之间的临时互连。 探针组件可以包括印刷在固定装置的表面上的电介质材料的基层。 固定装置的表面可以具有多个空腔。 多个离散的接触构件可以形成在固定装置中的多个空腔中并且耦合到基层。 多个导电迹线可以印刷到基底层的暴露表面上并与一个或多个离散接触构件的近端电耦合。 柔性层可以沉积在导电迹线和接触构件的近端上。 保护层可以沉积在柔性层上，使得当探针组件从固定装置移除时，接触构件的远端接触电路构件上的端子，并且导电迹线将电路构件电耦合到测试台。 探头组件上的电气设备可以与测试台通信以提供自适应测试。