公开(公告)号：US11728292B2

公开(公告)日：2023-08-15

申请号：US16779217

申请日：2020-01-31

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  I-Hsuan Peng ,  Nai-Wei Liu ,  Wei-Che Huang ,  Che-Ya Chou

IPC: H01L23/552 ,  H01L23/66 ,  H01L23/538 ,  H01L25/16 ,  H01L23/00 ,  H01L25/10 ,  H01L23/498

CPC classification number: H01L23/66 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L25/16 ,  H01L23/49816 ,  H01L25/105 ,  H01L2223/6677 ,  H01L2224/02379 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1421 ,  H01L2924/1435 ,  H01L2924/1438 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first redistribution layer (RDL) structure having a first surface and a second surface opposite to the first substrate. The first RDL structure includes a plurality of first conductive traces close to the first surface of the first RDL structure. An antenna pattern is disposed close to the second surface of the first RDL structure. A first semiconductor die is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. A plurality of conductive structures is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. The plurality of conductive structures is spaced apart from the antenna pattern through the plurality of first conductive traces of the first RDL structure.

公开(公告)号：US11410936B2

公开(公告)日：2022-08-09

申请号：US16983182

申请日：2020-08-03

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung Lin ,  Chia-Cheng Chang ,  I-Hsuan Peng ,  Nai-Wei Liu

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L23/043 ,  H01L23/13 ,  H01L23/538

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate having a first surface and a second surface opposite thereto, wherein the substrate includes a wiring structure, and a first semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure. The package further includes a second semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are separated by a molding material. A first hole and a second hole are formed on the second surface of the substrate. Finally, a frame is disposed over the first surface of the substrate, wherein the frame surrounds the first semiconductor die and the second semiconductor die.

公开(公告)号：US11222850B2

公开(公告)日：2022-01-11

申请号：US16846381

申请日：2020-04-12

Applicant: MEDIATEK INC.

Inventor： Yao-Chun Su ,  Chih-Jung Hsu ,  Yi-Jou Lin ,  I-Hsuan Peng

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/367 ,  H01L23/00 ,  H01L23/58 ,  H01L23/66 ,  H01L25/065

Abstract: An electronic package configured to operate at Gigabit-per-second (Gbps) data rates is disclosed. The electronic package includes a package substrate of a rectangular shape. A chip package having a first high-speed interface circuit die is mounted on a top surface of the package substrate. The chip package is rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through about 45 degrees. The first high-speed interface circuit die includes a first Serializer/Deserializer (SerDes) circuit block.

公开(公告)号：US10468341B2

公开(公告)日：2019-11-05

申请号：US16232129

申请日：2018-12-26

Applicant: MEDIATEK INC.

Inventor： Nai-Wei Liu ,  Tzu-Hung Lin ,  I-Hsuan Peng ,  Che-Hung Kuo ,  Che-Ya Chou ,  Wei-Che Huang

IPC: H01L23/485 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  H01L25/10

Abstract: A semiconductor package assembly includes a redistribution layer (RDL) structure, which RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace, and the RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The RDL structure includes a first region for a semiconductor die to be disposed thereon and a second region surrounding the first region, and the extended wing portion of the RDL contact pad is offset from a center of the first region.

公开(公告)号：US20190252351A1

公开(公告)日：2019-08-15

申请号：US16279925

申请日：2019-02-19

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  I-Hsuan Peng ,  Nai-Wei Liu ,  Ching-Wen Hsiao ,  Wei-Che Huang

IPC: H01L25/065 ,  H01L23/66 ,  H01L23/00 ,  H01L25/16 ,  H01L23/552 ,  H01L23/31 ,  H01L23/538 ,  H01L23/522

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/66 ,  H01L24/19 ,  H01L24/20 ,  H01L25/16 ,  H01L2223/6677 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1421 ,  H01L2924/1435 ,  H01L2924/1438 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025

Abstract: A semiconductor package structure including a first semiconductor package is provided. The first semiconductor package includes a first semiconductor package including a first redistribution layer (RDL) structure having a first surface and a second surface opposite thereto. A first semiconductor die and a first molding compound that surrounds the first semiconductor die are disposed on the first surface of the first RDL structure. An IMD structure having a conductive layer with an antenna pattern or a conductive shielding layer is disposed on the first molding compound and the first semiconductor die.

公开(公告)号：US10256210B2

公开(公告)日：2019-04-09

申请号：US15696247

申请日：2017-09-06

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Ching-Wen Hsiao ,  I-Hsuan Peng

IPC: H01L25/065 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L25/16 ,  H01L25/00 ,  H01L23/00 ,  H01L21/60

Abstract: A semiconductor package structure has a first electronic component on an insulating layer, a dielectric layer on the insulating layer and surrounding the first electronic component, a second electronic component stacked on the first electronic component, wherein an active surface of the first electronic component faces an active surface of the second electronic component, a molding compound on the first electronic component and surrounding the second electronic component, a third electronic component stacked on the second electronic component and the molding compound.

公开(公告)号：US10079192B2

公开(公告)日：2018-09-18

申请号：US15064545

申请日：2016-03-08

Applicant: MEDIATEK INC.

Inventor： Ching-Wen Hsiao ,  Tzu-Hung Lin ,  I-Hsuan Peng ,  Tung-Hsien Hsieh ,  Sheng-Ming Chang

IPC: H01L23/367 ,  H01L23/50 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/16 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/3675 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/00 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/02373 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92125 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor chip package assembly includes a package substrate having a chip mounting surface; a plurality of solder pads disposed on the chip mounting surface; a first dummy pad and a second dummy pad spaced apart from the first dummy pad disposed on the chip mounting surface; a solder mask on the chip mounting surface and partially covering the solder pads, the first dummy pad, and the second dummy pad; a chip package mounted on the chip mounting surface and electrically connected to the package substrate through a plurality of solder balls on respective said solder pads; a discrete device having a first terminal and a second terminal disposed between the chip package and the package substrate; a first solder connecting the first terminal with the first dummy pad and the chip package; and a second solder connecting the second terminal with the second dummy pad and the chip package.

公开(公告)号：US09997498B2

公开(公告)日：2018-06-12

申请号：US15624790

申请日：2017-06-16

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung Lin ,  Ching-Wen Hsiao ,  I-Hsuan Peng

IPC: H01L25/065 ,  H01L23/053 ,  H01L23/538 ,  H01L23/48 ,  H01L21/56 ,  H01L25/16 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/32265 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/92133 ,  H01L2225/06513 ,  H01L2225/06558 ,  H01L2225/06586 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/014

Abstract: In one implementation, a semiconductor package assembly includes a semiconductor die, a first molding compound covering a back surface of the semiconductor die, a redistribution layer (RDL) structure disposed on a front surface of the semiconductor die, wherein the semiconductor die is coupled to the RDL structure, and a passive device, embedded in the redistribution layer (RDL) structure and coupled to the semiconductor die.

公开(公告)号：US09786632B2

公开(公告)日：2017-10-10

申请号：US15184657

申请日：2016-06-16

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Ching-Wen Hsiao ,  I-Hsuan Peng

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L25/16 ,  H01L25/00 ,  H01L23/00 ,  H01L21/60

CPC classification number: H01L25/0652 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/97 ,  H01L25/16 ,  H01L25/50 ,  H01L2021/60015 ,  H01L2021/60232 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/10156 ,  H01L2224/11 ,  H01L2224/11013 ,  H01L2224/11019 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/24225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32501 ,  H01L2224/73267 ,  H01L2224/81 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00012

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first electronic component on a substrate. The semiconductor package structure also includes a second electronic component stacked on the first electronic component. The active surface of the first electronic component faces the active surface of the second electronic component. The semiconductor package structure further includes a molding compound on the first electronic component and surrounding the second electronic component. In addition, the semiconductor package structure includes a third electronic component stacked on the second electronic component and the molding compound.

公开(公告)号：US20160329262A1

公开(公告)日：2016-11-10

申请号：US15064545

申请日：2016-03-08

Applicant: MEDIATEK INC.

Inventor： Ching-Wen Hsiao ,  Tzu-Hung Lin ,  I-Hsuan Peng ,  Tung-Hsien Hsieh ,  Sheng-Ming Chang

IPC: H01L23/367 ,  H01L23/498 ,  H01L25/16 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/3675 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/02373 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92125 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor chip package assembly includes a package substrate having a chip mounting surface; a plurality of solder pads disposed on the chip mounting surface; a first dummy pad and a second dummy pad spaced apart from the first dummy pad disposed on the chip mounting surface; a solder mask on the chip mounting surface and partially covering the solder pads, the first dummy pad, and the second dummy pad; a chip package mounted on the chip mounting surface and electrically connected to the package substrate through a plurality of solder balls on respective said solder pads; a discrete device having a first terminal and a second terminal disposed between the chip package and the package substrate; a first solder connecting the first terminal with the first dummy pad and the chip package; and a second solder connecting the second terminal with the second dummy pad and the chip package.

Abstract translation: 半导体芯片封装组件包括具有芯片安装表面的封装衬底; 设置在芯片安装表面上的多个焊盘; 第一虚拟焊盘和与设置在芯片安装表面上的第一虚设焊盘间隔开的第二虚拟焊盘; 在芯片安装表面上的焊接掩模，并且部分地覆盖焊盘，第一虚拟焊盘和第二虚拟焊盘; 芯片封装，其安装在芯片安装表面上，并通过相应的所述焊盘上的多个焊球电连接到封装基板; 分立器件，其具有设置在所述芯片封装和所述封装衬底之间的第一端子和第二端子; 将所述第一端子与所述第一虚拟焊盘和所述芯片封装相连接的第一焊料; 以及将第二端子与第二虚拟焊盘和芯片封装件连接的第二焊料。