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    Fuses, and Methods of Forming and Using Fuses
    31.
    发明申请
    Fuses, and Methods of Forming and Using Fuses 审中-公开
    保险丝，以及使用保险丝的方法

    公开(公告)号：US20170047187A1

    公开(公告)日：2017-02-16

    申请号：US15339699

    申请日：2016-10-31

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Giorgio Servalli

    IPC: H01H85/06 ,  G11C13/00 ,  H01H85/08

    CPC classification number: H01H85/06 ,  G11C13/0004 ,  H01H37/32 ,  H01H85/08 ,  H01H85/11 ,  Y10T29/49107

    Abstract: Some embodiments include a fuse having a tungsten-containing structure directly contacting an electrically conductive structure. The electrically conductive structure may be a titanium-containing structure. An interface between the tungsten-containing structure and the electrically conductive structure is configured to rupture when current through the interface exceeds a predetermined level. Some embodiments include a method of forming and using a fuse. The fuse is formed to have a tungsten-containing structure directly contacting an electrically conductive structure. An interface between the tungsten-containing structure and the electrically conductive structure is configured to rupture when current through the interface exceeds a predetermined level. Current exceeding the predetermined level is passed through the interface to rupture the interface.

    Abstract translation: 一些实施例包括具有直接接触导电结构的含钨结构的熔丝。 导电结构可以是含钛结构。 含钨结构和导电结构之间的界面被配置为当通过界面的电流超过预定水平时破裂。 一些实施例包括形成和使用保险丝的方法。 保险丝形成为具有直接接触导电结构的含钨结构。 含钨结构和导电结构之间的界面被配置为当通过界面的电流超过预定水平时破裂。 超过预定水平的电流通过界面破裂界面。

    Memory cells, memory arrays, and methods of forming memory cells and arrays
    32.
    发明授权
    Memory cells, memory arrays, and methods of forming memory cells and arrays 有权
    存储单元，存储器阵列以及形成存储单元和阵列的方法

    公开(公告)号：US09484536B2

    公开(公告)日：2016-11-01

    申请号：US14799467

    申请日：2015-07-14

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Giorgio Servalli ,  Carmela Cupeta ,  Fabio Pellizzer

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1293 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1286 ,  H01L45/141 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1666 ,  H01L45/1675

    Abstract: Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. The phase change material is patterned into a plurality of confined structures, with the confined structures being in one-to-one correspondence with the heater structures and being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures. Some embodiments include memory arrays having heater structures over an array of electrical nodes. Confined phase change material structures are over the heater structures and in one-to-one correspondence with the heater structures. The confined phase change material structures are spaced from one another by one or more insulative materials that entirely laterally surround each of the confined phase change material structures.

    Abstract translation: 一些实施例包括形成存储器单元的方法。 加热器结构形成在电节点阵列上，相变材料跨过加热器结构形成。 相变材料被图案化成多个限制结构，其中限制结构与加热器结构一一对应，并且通过一个或多个完全横向围绕每个限制结构的绝缘材料彼此间隔开 。 一些实施例包括在电节点阵列上具有加热器结构的存储器阵列。 密闭相变材料结构在加热器结构之上，并且与加热器结构一一对应。 受限制的相变材料结构通过一个或多个完全横向围绕每个限定相变材料结构的绝缘材料彼此间隔开。

    PHASE CHANGE MEMORY APPARATUSES AND METHODS OF FORMING SUCH APPARATUSES
    34.
    发明申请
    PHASE CHANGE MEMORY APPARATUSES AND METHODS OF FORMING SUCH APPARATUSES 有权
    相变记忆装置和形成这种装置的方法

    公开(公告)号：US20150340408A1

    公开(公告)日：2015-11-26

    申请号：US14285286

    申请日：2014-05-22

    Applicant: Micron Technology, Inc.

    Inventor： Ugo Russo ,  Andrea Redaelli ,  Giorgio Servalli

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/141 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1608

    Abstract: Phase change memory apparatuses include memory cells including phase change material, bit lines electrically coupled to aligned groups of at least some of the memory cells, and heating elements electrically coupled to the phase change material of the memory cells. The heating elements include vertical portions extending in a bit line direction. Additional phase change memory apparatuses include dummy columns positioned between the memory columns and base contact columns. The dummy columns include phase change memory cells and lack heating elements coupled to the phase change memory cells thereof. Additional phase change memory apparatuses include heating elements operably coupled to phase change memory cells. An interfacial area between the heating elements and the phase change memory cells has a length that is independent of a bit line width. Methods relate to forming such phase change memory apparatuses.

    Abstract translation: 相变存储装置包括存储单元，其包括相变材料，电耦合到至少一些存储单元的对准组的位线以及电耦合到存储单元的相变材料的加热元件。 加热元件包括沿位线方向延伸的垂直部分。 附加的相变存储装置包括位于存储器列和基极接触柱之间的虚拟列。 虚拟列包括相变存储单元，并且没有耦合到其相变存储单元的加热元件。 附加的相变存储装置包括可操作地耦合到相变存储器单元的加热元件。 加热元件和相变存储器单元之间的界面面积具有与位线宽度无关的长度。 方法涉及形成这种相变存储装置。

    Memory Devices and Methods of Forming Memory Devices
    36.
    发明申请
    Memory Devices and Methods of Forming Memory Devices 有权

    公开(公告)号：US20250063722A1

    公开(公告)日：2025-02-20

    申请号：US18935844

    申请日：2024-11-04

    Applicant: Micron Technology, Inc.

    Inventor： Giorgio Servalli ,  Marcello Mariani

    IPC: H10B12/00 ,  G11C11/22 ,  H10B53/10 ,  H10B53/30

    Abstract: Some embodiments include an assembly having first and second pillars. Each of the pillars has an inner edge and an outer edge. A first gate is proximate a channel region of the first pillar. A second gate is proximate a channel region of the second pillar. A shield line is between the first and second pillars. First and second bottom electrodes are over the first and second pillars, respectively; and are configured as first and second angle plates. An insulative material is over the first and second bottom electrodes. The insulative material may be ferroelectric or non-ferroelectric. A top electrode is over the insulative material. Some embodiments include methods of forming assemblies.

    Techniques to manufacture ferroelectric memory devices
    37.
    发明授权
    Techniques to manufacture ferroelectric memory devices 有权

    公开(公告)号：US12211538B2

    公开(公告)日：2025-01-28

    申请号：US18203877

    申请日：2023-05-31

    Applicant: Micron Technology, Inc.

    Inventor： Giorgio Servalli ,  Marcello Mariani ,  Agostino Pirovano

    IPC: G11C11/22 ,  G11C5/06 ,  H01L29/51 ,  H10B53/10 ,  H10B53/20

    Abstract: Methods, systems, and devices for techniques to manufacture ferroelectric memory devices are described. In some cases, a memory array may be manufactured using a self-aligned manufacturing technique. For example, a continuous layer of dielectric material may be formed over an assembly which includes an array of transistors coupling contacts on the surface of the assembly with a set of digit lines. In some cases, an array of cavities may be etched into the dielectric material, each cavity exposing a set of contacts. A set of bottom electrodes corresponding to the set of contacts may be formed on sidewalls in each cavity, for example by depositing a layer of electrode material and etching the electrode material using a variety of hard masks.

    FERROELECTRIC MEMORY ARCHITECTURE WITH GAP REGION
    38.
    发明公开
    FERROELECTRIC MEMORY ARCHITECTURE WITH GAP REGION 审中-公开

    公开(公告)号：US20230397436A1

    公开(公告)日：2023-12-07

    申请号：US18204077

    申请日：2023-05-31

    Applicant: Micron Technology, Inc.

    Inventor： Giorgio Servalli ,  Marcello Mariani

    IPC: H10B53/30 ,  H10B53/40

    CPC classification number: H10B53/30 ,  G11C11/2273 ,  H10B53/40

    Abstract: Methods, systems, and devices for a ferroelectric memory architecture are described. A memory architecture may include a gap region between memory cells to reduce a capacitance between plates coupled with the memory cells. The gap region may include a fluid, such as air, which may have a relatively low dielectric constant to reduce a capacitance between plates and reduce (e.g., eliminate) undesirable coupling between plates during memory operations. Implementing the gap region between memory cells enables a memory device to increase speed and reduce resource consumption associated with memory operations

    Memory activation timing management
    39.
    发明授权
    Memory activation timing management 有权

    公开(公告)号：US11742002B2

    公开(公告)日：2023-08-29

    申请号：US17550535

    申请日：2021-12-14

    Applicant: Micron Technology, Inc.

    Inventor： Angelo Visconti ,  Daniele Balluchi ,  Giorgio Servalli

    IPC: G11C7/10 ,  G11C7/22 ,  G11C11/22

    CPC classification number: G11C7/1048 ,  G11C7/222 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2297

    Abstract: Systems, apparatuses, and methods related to memory activation timing management are described herein. In an examples, memory activation timing management can include receiving a first command associated with a set of memory cells, activating the set of memory cells to perform a memory access responsive to the first command, pre-charging the set of memory cells associated with the first command, receiving a second command associated with the set of memory cells, determining that the set of memory cells associated with the first command is a recently activated set of the plurality of sets of memory cells, imparting a delay, and applying a sensing voltage to the set of memory cells associated with the second command to perform a memory access responsive to the second command.

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