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    Memory device including self-aligned conductive contacts
    31.
    发明授权
    Memory device including self-aligned conductive contacts 有权

    公开(公告)号：US12218008B2

    公开(公告)日：2025-02-04

    申请号：US18200852

    申请日：2023-05-23

    Applicant: Micron Technology, Inc.

    Inventor： Kar Wui Thong ,  Harsh Narendrakumar Jain ,  John Hopkins

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H10B41/27 ,  H10B43/27

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes levels of conductive materials interleaved with levels of dielectric materials; memory cell strings including respective pillars extending through the levels of conductive materials and the levels of dielectric materials; a dielectric structure formed in a slit, the slit extending through the levels of conductive materials and the levels of dielectric materials, the dielectric structure separating the levels of conductive materials and the levels of dielectric materials into a first portion and a second portion; first conductive structures located over and coupled to respective pillars of the first memory cell strings; second conductive structures located over and coupled to respective pillars of the second memory cell strings; and a conductive line contacting the dielectric structure, a conductive structure of the first conductive structures, and a conductive structure of the second conductive structures.

    FLEXIBLE DESIGN AND PLACEMENT OF ALIGNMENT MARKS
    32.
    发明公开
    FLEXIBLE DESIGN AND PLACEMENT OF ALIGNMENT MARKS 审中-公开

    公开(公告)号：US20240297124A1

    公开(公告)日：2024-09-05

    申请号：US18593504

    申请日：2024-03-01

    Applicant: Micron Technology, Inc.

    Inventor： Shruthi Kumara Vadivel ,  Harsh Narendrakumar Jain ,  Lance David Williamson ,  Kaveri Jain ,  Adam Lewis Olson

    IPC: H01L23/544 ,  H01L21/308

    CPC classification number: H01L23/544 ,  H01L21/308 ,  H01L2223/54426

    Abstract: A memory device can include a substrate and a first alignment mark embedded in the substrate. The first alignment mark can be configured to a reference for a patterned second masking layer which is different from a first masking layer deposited on the substrate, and onto which the second patterned masking layer is deposited. The first masking layer can be an opaque or semi-opaque sacrificial layer and a second alignment mark can comprise at least a portion of the first masking layer. A location of the second alignment mark can correspond to a particular structure location in the substrate. The patterned second masking layer can include an additional alignment mark that is spaced laterally apart from the second alignment mark and the patterned second masking layer can define one or more locations of one or more structural features in the substrate.

    Memory Circuitry And Method Used In Forming Memory Circuitry
    36.
    发明公开
    Memory Circuitry And Method Used In Forming Memory Circuitry 审中-公开

    公开(公告)号：US20230395513A1

    公开(公告)日：2023-12-07

    申请号：US17865565

    申请日：2022-07-15

    Applicant: Micron Technology, Inc.

    Inventor： Harsh Narendrakumar Jain ,  Yiping Wang ,  Jordan Chess ,  Collin Howder

    IPC: H01L23/535 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

    CPC classification number: H01L23/535 ,  H01L23/5283 ,  H01L27/11556 ,  H01L27/11582

    Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers, with the stack extending from a memory-array region into a stair-step region. The stair-step region comprises a flight of stairs in a first vertical cross-section along a first direction. Masking material is formed directly above the flight of stairs. A species is ion implanted into the masking material to form different-composition first and second regions that are directly above individual of the stairs along a second direction that is orthogonal to the first direction. One of the first and the second regions is removed selectively relative to the other of the first and the second regions. After the removing, the other of the first and second regions is used as a mask while etching through one of the first tiers and one of the second tiers in the individual stairs to form multiple different-depth treads in the individual stairs in a second vertical cross-section along the second direction. Other embodiments, including structure, are disclosed.

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