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    Current summing monitoring circuit in a multi-chip package to control power
    31.
    发明授权
    Current summing monitoring circuit in a multi-chip package to control power 有权

    公开(公告)号：US10884480B1

    公开(公告)日：2021-01-05

    申请号：US16548699

    申请日：2019-08-22

    Applicant: Micron Technology, Inc.

    Inventor： Jonathan S. Parry ,  Stephen L. Miller ,  Liang Yu

    IPC: G11C5/14 ,  G06F1/3234 ,  G06F1/3225

    Abstract: A technique to provide power management for multiple dice. The technique provides for determining for each respective die of the multiple dice, power consumption for operating each respective die; and generating a respective analog current from each respective die that corresponds to the power consumption of each respective die. The technique further provides for driving each respective analog current onto a common node that results in a cumulative analog current; and utilizing the cumulative analog current at the common node to indicate total power consumption of the dice.

    Methods for independent memory bank maintenance and memory devices and systems employing the same
    34.
    发明授权
    Methods for independent memory bank maintenance and memory devices and systems employing the same 有权

    公开(公告)号：US10541017B2

    公开(公告)日：2020-01-21

    申请号：US16543477

    申请日：2019-08-16

    Applicant: Micron Technology, Inc.

    Inventor： George B. Raad ,  Jonathan S. Parry ,  James S. Rehmeyer ,  Timothy B. Cowles

    IPC: G11C7/00 ,  G11C11/406

    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

    Methods for independent memory bank maintenance and memory devices and systems employing the same
    36.
    发明授权
    Methods for independent memory bank maintenance and memory devices and systems employing the same 有权

    公开(公告)号：US10297307B1

    公开(公告)日：2019-05-21

    申请号：US15870657

    申请日：2018-01-12

    Applicant: Micron Technology, Inc.

    Inventor： George B. Raad ,  Jonathan S. Parry ,  James S. Rehmeyer ,  Timothy B. Cowles

    IPC: G11C7/00 ,  G11C11/406

    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

    TECHNIQUES FOR STAGGERING DATA BURST EVENTS ACROSS CHANNELS
    37.
    发明申请
    TECHNIQUES FOR STAGGERING DATA BURST EVENTS ACROSS CHANNELS 有权

    公开(公告)号：US20250117162A1

    公开(公告)日：2025-04-10

    申请号：US18771609

    申请日：2024-07-12

    Applicant: Micron Technology, Inc.

    Inventor： Liang Yu ,  Jonathan S. Parry

    IPC: G06F3/06

    Abstract: Methods, systems, and devices for techniques for staggering data burst events across channels are described. A memory system may offset data transfer events over multiple channels with a timing delay between data transfers over respective channels. For example, the memory system may initiate a first data transfer over a first channel at a first time and implement a timing delay before a second data transfer over a second channel at a second time such that the second time occurs after the first time. In some cases, the memory system may initiate one data transfer over each respective channel at a time, and in some cases, the memory system may initiate two or more data transfers over respective channels at a same time. In some cases, each channel may be associated with a respective timing delay.

    Adaptive throughput monitoring
    39.
    发明授权
    Adaptive throughput monitoring 有权

    公开(公告)号：US12204792B2

    公开(公告)日：2025-01-21

    申请号：US17396117

    申请日：2021-08-06

    Applicant: Micron Technology, Inc.

    Inventor： Reshmi Basu ,  David Aaron Palmer ,  Jonathan S. Parry

    IPC: G06F3/06 ,  G06F1/08

    Abstract: Methods, systems, and devices for adaptive throughput monitoring are described. In some examples, a memory system may be associated with one or more clocks that are each associated with a respective subcomponent. When the memory system receives a plurality of commands, the memory system may determine a throughput of the commands. Based on the determined throughput, the memory system may adjust a rate of one or more of the clocks.

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