公开(公告)号：US11538003B2

公开(公告)日：2022-12-27

申请号：US16988039

申请日：2020-08-07

Applicant: Oracle International Corporation

Inventor： Mark S. Moir ,  Harold Carr ,  Maurice P. Herlihy ,  Isaac Sheff

IPC: G06Q20/06 ,  G06Q20/38 ,  G06F16/27 ,  H04L9/32 ,  H04L9/00

Abstract: A sharded, permissioned, distributed ledger may reduce the amount of work and communication required by each participant, thus possibly avoiding scalability bottlenecks that may be inherent in previous distributed ledger implementations and possibly enabling the use of additional resources to translate to increased throughput. A sharded, permissioned, distributed ledger may be made up of multiple shards, each of which may also be a distributed ledger and which may operate in parallel. Participation within a sharded, permissioned, distributed ledger may be allowed only with permission of an authority. A sharded, permissioned, distributed ledger may include a plurality of nodes, each including a dispatcher configured to receive transaction requests from clients and to forward received requests to verifiers configured to append transactions to individual ones of the shards.

公开(公告)号：US10776154B2

公开(公告)日：2020-09-15

申请号：US14697510

申请日：2015-04-27

Applicant: Oracle International Corporation

Inventor： David Dice ,  Mark S. Moir

IPC: G06F12/08 ,  G06F9/46 ,  G06F9/54 ,  G06F9/30 ,  G06F12/0808 ,  G06F12/0815

Abstract: In shared-memory computer systems, threads may communicate with one another using shared memory. A receiving thread may poll a message target location repeatedly to detect the delivery of a message. Such polling may cause excessive cache coherency traffic and/or congestion on various system buses and/or other interconnects. A method for inter-processor communication may reduce such bus traffic by reducing the number of reads performed and/or the number of cache coherency messages necessary to pass messages. The method may include a thread reading the value of a message target location once, and determining that this value has been modified by detecting inter-processor messages, such as cache coherence messages, indicative of such modification. In systems that support transactional memory, a thread may use transactional memory primitives to detect the cache coherence messages. This may be done by starting a transaction, reading the target memory location, and spinning until the transaction is aborted.

公开(公告)号：US20170236120A1

公开(公告)日：2017-08-17

申请号：US15169622

申请日：2016-05-31

Applicant: Oracle International Corporation

Inventor： Maurice P. Herlihy ,  Mark S. Moir

IPC: G06Q20/38

CPC classification number: G06Q20/3827 ,  G06F21/57 ,  G06F21/602 ,  G06F2221/2101 ,  G06Q20/065 ,  G06Q20/3821 ,  G06Q2220/00 ,  H04L9/3236 ,  H04L2209/38

Abstract: Distributed ledger systems that provide enhanced accountability and trust are described. A sender node may send messages to a receiver node. The sender node may compute a value (e.g., a hash) based on the sent messages and at least one previously sent message. The sender node may receive a confirmation message for the messages from the receiver node including a value computed by the receiver node based on the messages and at least one previously received message. The sender node may compare the computed value to the value included in the confirmation message to determine that the receiver node has or has not received a correct sequence of messages. The confirmation message may also include a summary of local data of the receiver node that indicates to the sender node that the receiver node has or has not processed all messages received.

公开(公告)号：US09417910B2

公开(公告)日：2016-08-16

申请号：US13722839

申请日：2012-12-20

Applicant: Oracle International Corporation

Inventor： David Dice ,  Yosef Lev ,  Mark S. Moir

IPC: G06F9/30 ,  G06F9/48 ,  G06F9/52

CPC classification number: G06F9/4881 ,  G06F9/52 ,  G06F9/524

Abstract: The systems and methods described herein may implement probabilistic counters and/or update mechanisms for those counters such that they are dependent on the value of a configurable accuracy parameter. The accuracy parameter value may be adjusted to provide fine-grained control over the tradeoff between the accuracy of the counters and the performance of applications that access them. The counters may be implemented as data structures that include a mantissa portion and an exponent portion that collectively represent an update probability value. When updating the counters, the value of the configurable accuracy parameter may affect whether, when, how often, or by what amount the mantissa portion and/or the exponent portion are updated. Updating a probabilistic counter may include multiplying its value by a constant that is dependent on the value of a configurable accuracy parameter. The counters may be accessible within transactions. The counters may have deterministic update policies.

Abstract translation: 这里描述的系统和方法可以为这些计数器实现概率计数器和/或更新机制，使得它们取决于可配置精度参数的值。 可以调整精度参数值，以便在计数器的准确性和访问它们的应用程序的性能之间进行权衡，以提供细粒度的控制。 计数器可以被实现为数据结构，其包括统一地表示更新概率值的尾数部分和指数部分。 当更新计数器时，可配置的精度参数的值可能会影响是否，何时，多长时间还是影响尾数部分和/或指数部分的更新量。 更新概率计数器可以包括将其值乘以一个取决于可配置精度参数的值的常数。 柜台可能在交易中可访问。 计数器可能具有确定性的更新策略。

公开(公告)号：US20160011915A1

公开(公告)日：2016-01-14

申请号：US14736123

申请日：2015-06-10

Applicant: Oracle International Corporation

Inventor： David Dice ,  Timothy L. Harris ,  Alex Kogan ,  Yosef Lev ,  Mark S. Moir

IPC: G06F9/52

Abstract: Transactional Lock Elision allows hardware transactions to execute unmodified critical sections protected by the same lock concurrently, by subscribing to the lock and verifying that it is available before committing the transaction. A “lazy subscription” optimization, which delays lock subscription, can potentially cause behavior that cannot occur when the critical sections are executed under the lock. Hardware extensions may provide mechanisms to ensure that lazy subscriptions are safe (e.g., that they result in correct behavior). Prior to executing a critical section transactionally, its lock and subscription code may be identified (e.g., by writing their locations to special registers). Prior to committing the transaction, the thread executing the critical section may verify that the correct lock was correctly subscribed to. If not, or if locations identified by the special registers have been modified, the transaction may be aborted. Nested critical sections associated with different lock types may invoke different subscription code.

Abstract translation: 事务锁定Elision允许硬件事务通过订阅锁并在提交事务之前验证它是否可用来同时执行受同一锁定保护的未修改的关键段。 延迟锁订阅的“延迟订阅”优化可能会导致在锁定下执行关键部分时不会发生的行为。 硬件扩展可以提供机制来确保延迟订阅是安全的（例如，它们导致正确的行为）。 在事务执行关键部分之前，可以识别其锁定和订阅代码（例如，通过将其位置写入特殊寄存器）。 在提交事务之前，执行关键部分的线程可能会验证正确锁定是否正确。 如果不是，或者如果由特殊寄存器识别的位置已被修改，则可能会中止该事务。 与不同锁类型相关联的嵌套关键部分可能会调用不同的订阅代码。

公开(公告)号：US09110718B2

公开(公告)日：2015-08-18

申请号：US13625700

申请日：2012-09-24

Applicant: Oracle International Corporation

Inventor： Mark S. Moir ,  David Dice ,  Paul N. Loewenstein

IPC: G06F9/50 ,  G06F12/08

CPC classification number: G06F9/50 ,  G06F9/5066 ,  G06F9/544 ,  G06F12/0888

Abstract: The present embodiments provide a system for supporting targeted stores in a shared-memory multiprocessor. A targeted store enables a first processor to push a cache line to be stored in a cache memory of a second processor in the shared-memory multiprocessor. This eliminates the need for multiple cache-coherence operations to transfer the cache line from the first processor to the second processor. The system includes an interface, such as an application programming interface (API), and a system call interface or an instruction-set architecture (ISA) that provides access to a number of mechanisms for supporting targeted stores. These mechanisms include a thread-location mechanism that determines a location near where a thread is executing in the shared-memory multiprocessor, and a targeted-store mechanism that targets a store to a location (e.g., cache memory) in the shared-memory multiprocessor.

Abstract translation: 本实施例提供一种用于在共享存储器多处理器中支持目标存储的系统。 目标商店使得第一处理器能够将存储在共享存储器多处理器中的第二处理器的高速缓冲存储器中的高速缓存行推送。 这消除了对多个高速缓存相干操作的需要，以将高速缓存行从第一处理器传送到第二处理器。 该系统包括诸如应用编程接口（API）的接口以及提供对用于支持目标商店的多种机制的访问的系统调用接口或指令集架构（ISA）。 这些机制包括一个线程定位机制，它确定线程在共享存储器多处理器中执行的位置附近的位置，以及将存储器定位到共享存储器多处理器中的位置（例如高速缓冲存储器）的目标存储机制 。

公开(公告)号：US20140181423A1

公开(公告)日：2014-06-26

申请号：US13722817

申请日：2012-12-20

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： David Dice ,  Yosef Lev ,  Mark S. Moir

IPC: G06F13/18

CPC classification number: G06F13/18 ,  G06F9/5027 ,  G06F9/52 ,  G06F9/526

Abstract: The systems and methods described herein may be used to implement scalable statistics counters suitable for use in systems that employ a NUMA style memory architecture. The counters may be implemented as data structures that include a count value portion and a node identifier portion. The counters may be accessible within transactions. The node identifier portion may identify a node on which a thread that most recently incremented the counter was executing or one on which a thread that has requested priority to increment the shared counter was executing. Threads executing on identified nodes may have higher priority to increment the counter than other threads. Threads executing on other nodes may delay their attempts to increment the counter, thus encouraging consecutive updates from threads on a single node. Impatient threads may attempt to update the node identifier portion or may update an anti-starvation variable to indicate a request for priority.

Abstract translation: 本文描述的系统和方法可以用于实现适用于采用NUMA风格存储器架构的系统中的可伸缩统计计数器。 计数器可以被实现为包括计数值部分和节点标识符部分的数据结构。 柜台可能在交易中可访问。 节点标识符部分可以标识正在执行计数器最近递增的线程的节点，或者正在执行已经请求优先级以增加共享计数器的线程的节点。 在标识节点上执行的线程可能比其他线程具有更高的优先级来增加计数器。 在其他节点上执行的线程可能会延迟其增加计数器的尝试，从而鼓励单个节点上线程的连续更新。 不耐烦的线程可以尝试更新节点标识符部分，或者可以更新反饥饿变量以指示优先级请求。