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公开(公告)号：US20190214341A1
公开(公告)日：2019-07-11
申请号：US16242529
申请日：2019-01-08
Inventor： Abderrezak MARZAKI , Arnaud REGNIER , Stephan NIEL
IPC: H01L23/522 , H01L21/8238 , H01L21/762 , H01L21/02
CPC classification number: H01L23/5223 , H01L21/0214 , H01L21/76224 , H01L21/823878 , H01L21/823892 , H01L27/0805 , H01L29/66181 , H01L29/945
Abstract: A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.
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公开(公告)号：US20230326883A1
公开(公告)日：2023-10-12
申请号：US18210286
申请日：2023-06-15
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Abderrezak MARZAKI , Pascal FORNARA
CPC classification number: H01L23/573 , G04F1/005 , H01L21/705 , H01L27/013 , H01L27/101
Abstract: An ultralong time constant time measurement device includes elementary capacitive elements that are connected in series. Each elementary capacitive element is formed by a stack of a first conductive region, a dielectric layer having a thickness suited for allowing charge to flow by direct tunnelling effect, and a second conductive region. The first conductive region is housed in a trench extending from a front face of a semiconductor substrate down into the semiconductor substrate. The dielectric layer rests on the first face of the semiconductor substrate and in particular on a portion of the first conductive region in the trench. The second conductive region rests on the dielectric layer.
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公开(公告)号：US20230119204A1
公开(公告)日：2023-04-20
申请号：US18082155
申请日：2022-12-15
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Alexandre SARAFIANOS , Abderrezak MARZAKI
Abstract: A semiconductor substrate includes a buried semiconductor layer and semiconductor wells. A device for detecting a possible thinning of the semiconductor substrate via the rear face thereof is formed on and in the semiconductor wells. The device is a non-inverting buffer including an input terminal and an output terminal, the device being powered between a supply terminal and a reference terminal where the buried semiconductor layer provides the supply terminal. A control circuit delivers an input signal in a first state to the input terminal and outputs a control signal indicating a detection of a thinning of the substrate if a signal generated at the output terminal in response to the input signal is in a second state different from the first state.
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公开(公告)号：US20220028863A1
公开(公告)日：2022-01-27
申请号：US17493226
申请日：2021-10-04
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Abderrezak MARZAKI
IPC: H01L27/108 , H01L27/11521 , H01L49/02 , H01L29/66 , H01L29/94
Abstract: A capacitive element is located in an active region of the substrate and on a front face of the substrate. The capacitive element includes a first electrode and a second electrode. The first electrode is formed by a first conductive region and the active region. The second electrode is formed by a second conductive region and a monolithic conductive region having one part covering a surface of said front face and at least one part extending into the active region perpendicularly to said front face. The first conductive region is located between and is insulated from the monolithic conductive region and a second conductive region.
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公开(公告)号：US20210225757A1
公开(公告)日：2021-07-22
申请号：US17226324
申请日：2021-04-09
Inventor： Abderrezak MARZAKI , Arnaud REGNIER , Stephan NIEL
IPC: H01L23/522 , H01L49/02 , H01L27/11524
Abstract: First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.
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Patent Agency Ranking
公开(公告)号：US20210167009A1
公开(公告)日：2021-06-03
申请号：US17173275
申请日：2021-02-11
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Abderrezak MARZAKI
IPC: H01L23/522 , H01L27/08 , H01L21/762 , H01L29/66
Abstract: A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.
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37.发明申请公开(公告)号：US20210005613A1
公开(公告)日：2021-01-07
申请号：US17026874
申请日：2020-09-21
Inventor： Abderrezak MARZAKI , Arnaud REGNIER , Stephan NIEL , Quentin HUBERT , Thomas CABOUT
IPC: H01L27/108 , H01L29/66 , H01L49/02 , H01L29/94
Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.
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38.发明申请公开(公告)号：US20210005612A1
公开(公告)日：2021-01-07
申请号：US17026869
申请日：2020-09-21
Inventor： Abderrezak MARZAKI , Arnaud REGNIER , Stephan NIEL , Quentin HUBERT , Thomas CABOUT
IPC: H01L27/108 , H01L29/66 , H01L49/02 , H01L29/94
Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.
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39.发明申请公开(公告)号：US20200286986A1
公开(公告)日：2020-09-10
申请号：US16802871
申请日：2020-02-27
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Abderrezak MARZAKI
IPC: H01L49/02 , H01L27/11521 , H01L27/11531 , H01L29/423 , H01L29/788 , H01L29/66
Abstract: A semiconductor substrate has a front face with a first dielectric region. A capacitive element includes, on a surface of the first dielectric region at the front face, a stack of layers which include a first conductive region, a second conductive region and a third conductive region. The second conductive region is electrically insulated from the first conductive region by a second dielectric region. The second conductive region is further electrically insulated from the third conductive region by a third dielectric region. The first and third conductive regions form one plate of the capacitive element, and the second conductive region forms another plate of the capacitive element.
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公开(公告)号：US20200286896A1
公开(公告)日：2020-09-10
申请号：US16803226
申请日：2020-02-27
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Abderrezak MARZAKI
IPC: H01L27/108 , H01L49/02 , H01L29/66 , H01L29/94 , H01L27/11521
Abstract: A capacitive element is located in an active region of the substrate and on a front face of the substrate. The capacitive element includes a first electrode and a second electrode. The first electrode is formed by a first conductive region and the active region. The second electrode is formed by a second conductive region and a monolithic conductive region having one part covering a surface of said front face and at least one part extending into the active region perpendicularly to said front face. The first conductive region is located between and is insulated from the monolithic conductive region and a second conductive region.
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