公开(公告)号：US11983025B2

公开(公告)日：2024-05-14

申请号：US17967498

申请日：2022-10-17

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Mayankkumar Hareshbhai Niranjani ,  Dhulipalla Phaneendra Kumar ,  Gourav Garg ,  Sourabh Banzal

IPC: G05F1/10 ,  G05F1/46 ,  G05F3/02 ,  H03K19/20

CPC classification number: G05F1/46 ,  H03K19/20

Abstract: An electric device includes: a first power domain; a second power domain; a third power domain, where during power-up, the third, the second, and the first power domains are configured to be powered up sequentially, where during standby-exit, the first, the second, and the third power domains are configured to be powered up sequentially; isolation paths that provide controlled signal transmission among the first, the second, and the third power domains, where each isolation path includes an isolation circuit between an input power domain and an output power domain of the isolation path; and a control circuit in the first power domain, where for each isolation path, the control circuit is configured to generate an isolation control signal for the isolation circuit, where the isolation circuit is configured enable or disable signal transmission along the isolation path.

公开(公告)号：US20220276302A1

公开(公告)日：2022-09-01

申请号：US17663561

申请日：2022-05-16

Applicant: STMicroelectronics International N.V.

Inventor： Rajesh Narwal ,  Venkata Narayanan Srinivasan ,  Srinivas Dhulipalla

IPC: G01R31/30 ,  G01R31/3173 ,  G01R31/319 ,  G01R31/317

Abstract: Circuits and methods for testing voltage monitor circuits are provided. In one embodiment, a method includes setting voltage monitor circuits to test mode; setting, a monitor reference in each voltage monitor circuit, to a respective targeted threshold voltage using a corresponding trim code; ramping, a voltage provided to a subset of voltage monitor circuits, from a first voltage to a second voltage using a test voltage supply, voltages between the first voltage and the second voltage corresponding with targeted threshold voltages of the subset of voltage monitor circuits; determining, for each voltage monitor circuit in the subset of voltage monitor circuits, a voltage value of the test voltage supply resulting in a change in a logic state at an output of a corresponding voltage monitor circuit.

公开(公告)号：US11340292B2

公开(公告)日：2022-05-24

申请号：US16506264

申请日：2019-07-09

Applicant: STMicroelectronics International N.V.

Inventor： Rajesh Narwal ,  Venkata Narayanan Srinivasan ,  Srinivas Dhulipalla

IPC: G01R31/30 ,  G01R31/3173 ,  G01R31/317 ,  G01R31/319

Abstract: Circuits and methods for testing voltage monitor circuits are provided. In one embodiment, a method includes setting voltage monitor circuits to test mode; setting, a monitor reference in each voltage monitor circuit, to a respective targeted threshold voltage using a corresponding trim code; ramping, a voltage provided to a subset of voltage monitor circuits, from a first voltage to a second voltage using a test voltage supply, voltages between the first voltage and the second voltage corresponding with targeted threshold voltages of the subset of voltage monitor circuits; determining, for each voltage monitor circuit in the subset of voltage monitor circuits, a voltage value of the test voltage supply resulting in a change in a logic state at an output of a corresponding voltage monitor circuit.

公开(公告)号：US20210011080A1

公开(公告)日：2021-01-14

申请号：US16506264

申请日：2019-07-09

Applicant: STMicroelectronics International N.V.

Inventor： Rajesh Narwal ,  Venkata Narayanan Srinivasan ,  Srinivas Dhulipalla

IPC: G01R31/30 ,  G01R31/3173 ,  G01R31/317 ,  G01R31/319

Abstract: Circuits and methods for testing voltage monitor circuits are provided. In one embodiment, a method includes setting voltage monitor circuits to test mode; setting, a monitor reference in each voltage monitor circuit, to a respective targeted threshold voltage using a corresponding trim code; ramping, a voltage provided to a subset of voltage monitor circuits, from a first voltage to a second voltage using a test voltage supply, voltages between the first voltage and the second voltage corresponding with targeted threshold voltages of the subset of voltage monitor circuits; determining, for each voltage monitor circuit in the subset of voltage monitor circuits, a voltage value of the test voltage supply resulting in a change in a logic state at an output of a corresponding voltage monitor circuit.

公开(公告)号：US10890619B2

公开(公告)日：2021-01-12

申请号：US16505174

申请日：2019-07-08

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Manish Sharma

IPC: G01R31/317 ,  G01R31/3185

Abstract: A JTAG interface in an IC includes a test mode select (TMS) pin receiving a TMS signal, a testing test access port (TAP) having a TMS signal input, a debugging test access port (TAP) having a TMS signal and glue logic coupled to receive a first output from the testing TAP and a second output from the debugging TAP. A flip-flop receives input from the testing TAP and the debugging TAP through the glue logic. A first AND gate has output coupled to the TMS signal input of the debugging TAP, and receives input from an output of the flip-flop and the TMS signal. An inverter has an input coupled to receive input from the flip-flop. A second AND gate has output coupled to the TMS signal input of the testing TAP, and receives input from the TMS signal and output of the inverter.

公开(公告)号：US10802077B1

公开(公告)日：2020-10-13

申请号：US16387809

申请日：2019-04-18

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Shiv Kumar Vats ,  Himanshu

IPC: G01R31/3185 ,  G01R31/3183 ,  G01R31/3187

Abstract: A test circuit includes a BIST clock generator and a functional clock generator. A first multiplexer selectively passes the BIST clock or the functional clock as a selected clock in response to a clock selection signal. BIST logic operates based upon the BIST clock. Functional logic operating based upon the functional clock signal. A memory operates based upon the selected clock. When the test circuit is operating in BIST mode, a clock selection circuit receives and passes a BIST signal as the clock selection signal. When the test circuit is operating in a shift phase of a scan test mode, it generates the clock selection signal as asserted, and when the test circuit is operating in the capture phase of the scan test mode, it generates the clock signal as equal to a last bit received from a scan chain.

公开(公告)号：US10747282B2

公开(公告)日：2020-08-18

申请号：US16162543

申请日：2018-10-17

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Srinivas Dhulipalla ,  Sandip Atal

IPC: G06F1/24 ,  H03K19/00 ,  G01R31/319 ,  G06F1/3206 ,  H03K17/22

Abstract: An electronic device includes a power management circuit generating output for a plurality of voltage monitors that each detect whether voltages received from a test apparatus are at least a different minimum threshold. The power management circuit also generates a test enable signal indicative of whether the test apparatus is supplying the minimum required voltages to the electronic device. A control circuit receives the output for the plurality of voltage monitors and the test enable signal and generates at least one control signal as a function of the output for the plurality of voltage monitors and the test enable signal. An output circuit receives the at least one control signal and generates an interface control signal that selectively enables or disables interface with analog intellectual property packages within the electronic device, in response to the at least one control signal.

公开(公告)号：US12203982B2

公开(公告)日：2025-01-21

申请号：US17663561

申请日：2022-05-16

Applicant: STMicroelectronics International N.V.

Inventor： Rajesh Narwal ,  Venkata Narayanan Srinivasan ,  Srinivas Dhulipalla

IPC: G01R31/30 ,  G01R31/317 ,  G01R31/3173 ,  G01R31/319

Abstract: Circuits and methods for testing voltage monitor circuits are provided. In one embodiment, a method includes setting voltage monitor circuits to test mode; setting, a monitor reference in each voltage monitor circuit, to a respective targeted threshold voltage using a corresponding trim code; ramping, a voltage provided to a subset of voltage monitor circuits, from a first voltage to a second voltage using a test voltage supply, voltages between the first voltage and the second voltage corresponding with targeted threshold voltages of the subset of voltage monitor circuits; determining, for each voltage monitor circuit in the subset of voltage monitor circuits, a voltage value of the test voltage supply resulting in a change in a logic state at an output of a corresponding voltage monitor circuit.

公开(公告)号：US20240402249A1

公开(公告)日：2024-12-05

申请号：US18203345

申请日：2023-05-30

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Manish Sharma ,  Jeena Mary George ,  Umesh Chandra Srivastava

IPC: G01R31/3185

Abstract: According to an embodiment, a method for testing a triple-voting flop (TVF) is provided. The method includes providing a first and a second scan enable signal by a control circuit to, respectively, a first scan flip-flop and a third scan flip-flop of the TVF; receiving a third scan enable signal at the second scan flip-flop of the TVF; providing a scan input signal to the first scan flip-flop, the second scan flip-flop, and the third scan flip-flop; controlling the first scan enable signal, the second scan enable signal, and the third scan enable signal; receiving, at an output of the TVF, a scan output signal; and determining whether the TVF suffers from a fault based on the scan output signal and the controlling of the first scan enable signal, the second scan enable signal, and the third scan enable signal.

公开(公告)号：US20240012051A1

公开(公告)日：2024-01-11

申请号：US18448265

申请日：2023-08-11

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Shiv Kumar Vats ,  Tripti Gupta

IPC: G01R31/3177 ,  G01R31/317 ,  G06F1/04

CPC classification number: G01R31/3177 ,  G01R31/31724 ,  G01R31/31727 ,  G06F1/04

Abstract: In an embodiment, a method for performing scan includes: entering scan mode; receiving a test pattern; applying the test pattern through a first scan chain by asserting and deasserting a scan enable signal to respectively perform shift and capture operations to the first scan chain; while applying the test pattern through the first scan chain, controlling a further scan flip-flop with the first scan chain without transitioning a further scan enable input of the further scan flip-flop; and evaluating an output of the first scan chain to detect faults.