公开(公告)号：US20240402249A1

公开(公告)日：2024-12-05

申请号：US18203345

申请日：2023-05-30

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Manish Sharma ,  Jeena Mary George ,  Umesh Chandra Srivastava

IPC: G01R31/3185

Abstract: According to an embodiment, a method for testing a triple-voting flop (TVF) is provided. The method includes providing a first and a second scan enable signal by a control circuit to, respectively, a first scan flip-flop and a third scan flip-flop of the TVF; receiving a third scan enable signal at the second scan flip-flop of the TVF; providing a scan input signal to the first scan flip-flop, the second scan flip-flop, and the third scan flip-flop; controlling the first scan enable signal, the second scan enable signal, and the third scan enable signal; receiving, at an output of the TVF, a scan output signal; and determining whether the TVF suffers from a fault based on the scan output signal and the controlling of the first scan enable signal, the second scan enable signal, and the third scan enable signal.

公开(公告)号：US12265124B1

公开(公告)日：2025-04-01

申请号：US18474511

申请日：2023-09-26

Applicant: STMicroelectronics International N.V.

Inventor： Sandeep Jain ,  Akshay Kumar Jain ,  Jeena Mary George

IPC: G01R31/319 ,  G01R31/317 ,  G01R31/3193

Abstract: According to an embodiment, a digital circuit with N number of redundant flip-flops is provided, each having a data input coupled to a common data signal. The digital circuit operates in a functional mode and a test mode. During test mode, a first flip-flop is arranged as part of a test path and N−1 flip-flops are arranged as shadow logic. A test pattern at the common data signal is provided and a test output signal is observed at an output terminal of the first flip-flop to determine faults within a test path of the first flip-flop. At the same cycle, the test output signals of each of the N−1 number of redundant flip-flops is observed through the functional path to determine faults.

公开(公告)号：US20230327674A1

公开(公告)日：2023-10-12

申请号：US17719004

申请日：2022-04-12

Applicant: STMicroelectronics International N.V.

Inventor： Sandeep Jain ,  Jeena Mary George

IPC: G01R31/3185 ,  H03K3/037 ,  H03K19/00 ,  H03K19/20

CPC classification number: G01R31/318536 ,  H03K3/037 ,  H03K19/0021 ,  H03K19/20 ,  G01R31/318525

Abstract: In an embodiment, an integrated circuit includes: a voting circuit including N scan flip-flops, where N is an odd number greater than or equal to 3, and where the N scan flip-flops includes a first scan flip-flop and a second scan flip-flop, where an output of the first scan flip-flop is coupled to a scan input of the second scan flip-flop; a scan chain including the N scan flip-flops of the voting circuit, and third and fourth scan flip-flops, the scan chain configured to receive a scan enable signal; and a scan enable control circuit configured to control a scan enable input of the first or second scan flip-flops based on the scan enable signal and based on a scan input of the third scan flip-flop or an output of the fourth scan flip-flop.

公开(公告)号：US12146911B1

公开(公告)日：2024-11-19

申请号：US18203345

申请日：2023-05-30

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Manish Sharma ,  Jeena Mary George ,  Umesh Chandra Srivastava

IPC: G01R31/3185

Abstract: According to an embodiment, a method for testing a triple-voting flop (TVF) is provided. The method includes providing a first and a second scan enable signal by a control circuit to, respectively, a first scan flip-flop and a third scan flip-flop of the TVF; receiving a third scan enable signal at the second scan flip-flop of the TVF; providing a scan input signal to the first scan flip-flop, the second scan flip-flop, and the third scan flip-flop; controlling the first scan enable signal, the second scan enable signal, and the third scan enable signal; receiving, at an output of the TVF, a scan output signal; and determining whether the TVF suffers from a fault based on the scan output signal and the controlling of the first scan enable signal, the second scan enable signal, and the third scan enable signal.

公开(公告)号：US20250102574A1

公开(公告)日：2025-03-27

申请号：US18474511

申请日：2023-09-26

Applicant: STMicroelectronics International N.V.

Inventor： Sandeep Jain ,  Akshay Kumar Jain ,  Jeena Mary George

IPC: G01R31/319 ,  G01R31/317 ,  G01R31/3193

Abstract: According to an embodiment, a digital circuit with N number of redundant flip-flops is provided, each having a data input coupled to a common data signal. The digital circuit operates in a functional mode and a test mode. During test mode, a first flip-flop is arranged as part of a test path and N-1 flip-flops are arranged as shadow logic. A test pattern at the common data signal is provided and a test output signal is observed at an output terminal of the first flip-flop to determine faults within a test path of the first flip-flop. At the same cycle, the test output signals of each of the N-1 number of redundant flip-flops is observed through the functional path to determine faults.

公开(公告)号：US11848672B2

公开(公告)日：2023-12-19

申请号：US17719004

申请日：2022-04-12

Applicant: STMicroelectronics International N.V.

Inventor： Sandeep Jain ,  Jeena Mary George

IPC: H03K19/23 ,  G01R31/3185 ,  H03K19/20 ,  H03K19/00 ,  H03K3/037

CPC classification number: H03K19/23 ,  G01R31/318525 ,  G01R31/318536 ,  H03K3/037 ,  H03K19/0021 ,  H03K19/20

Abstract: In an embodiment, an integrated circuit includes: a voting circuit including N scan flip-flops, where N is an odd number greater than or equal to 3, and where the N scan flip-flops includes a first scan flip-flop and a second scan flip-flop, where an output of the first scan flip-flop is coupled to a scan input of the second scan flip-flop; a scan chain including the N scan flip-flops of the voting circuit, and third and fourth scan flip-flops, the scan chain configured to receive a scan enable signal; and a scan enable control circuit configured to control a scan enable input of the first or second scan flip-flops based on the scan enable signal and based on a scan input of the third scan flip-flop or an output of the fourth scan flip-flop.