公开(公告)号：US09786372B2

公开(公告)日：2017-10-10

申请号：US15172929

申请日：2016-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Wan Nam ,  Sun-Min Yun ,  Bongsoon Lim ,  Yoon-Hee Choi

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/04 ,  G11C16/28 ,  G11C8/08 ,  G11C16/34

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/28 ,  G11C16/3459

Abstract: According to example embodiments of inventive concepts, a nonvolatile memory device includes a memory cell array, an address decoder, an input/output circuit, a voltage generation circuit, and control logic. The memory cell array includes a plurality of memory blocks on a substrate. Each of the memory blocks includes a plurality of strings connected between bit lines and a common source line. The address decoder is configured to measure impedance information of word lines of a selected memory block. The voltage generation circuit is configured to generate word line voltages to be applied to word lines, and at least one of the word line voltages includes an offset voltage and a target voltage. The control logic is configured to adjust a level of the offset voltage and the offset time depending on the measured impedance information of the word lines.

公开(公告)号：US12282664B2

公开(公告)日：2025-04-22

申请号：US18314978

申请日：2023-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heeseok Eun ,  Jinwook Lee ,  Bongsoon Lim

IPC: G06F3/06

Abstract: A method is provided to operate a storage device including a storage controller and a plurality of nonvolatile memory devices. A plurality of original data blocks are received at the storage controller from a host. An original parity block is generated based on the original data blocks. The original data blocks and the original parity block are stored in respective ones of the nonvolatile memory devices, wherein a first original data block of the original data blocks is stored in a first one of the nonvolatile memory devices, and wherein the original parity block is stored in a second one of the nonvolatile memory devices. A new data block corresponding to the first original data block is received at the storage controller from the host after storing the original data blocks and the original parity block. The new data block is stored in the first nonvolatile memory device. A new parity block is generated at the second nonvolatile memory device based on the original parity block and based on differences between the first original data block and the new data block.

公开(公告)号：US12224277B2

公开(公告)日：2025-02-11

申请号：US18149206

申请日：2023-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk Choi ,  Bongsoon Lim ,  Hongsoo Jeon ,  Jaeduk Yu

IPC: H01L23/528 ,  G11C16/04 ,  G11C16/08 ,  H01L23/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L27/112

Abstract: A memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines and bitlines, an upper substrate, and a memory cell array. The memory cell array includes a memory blocks. The second semiconductor layer includes a lower substrate, and an address decoder. Each memory block includes a core region including a memory cells, a first extension region adjacent to a first side of the core region and including a plurality of wordline contacts, and a second extension region adjacent to a second side of the core region and including an insulating mold structure. The second extension region includes step zones and at least one flat zone. Through-hole vias penetrating the insulating mold structure are in the flat zone. The wordlines and the address decoder are electrically connected with each other by at least the through-hole vias.

公开(公告)号：US12120881B2

公开(公告)日：2024-10-15

申请号：US16931500

申请日：2020-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bongsoon Lim ,  Daeseok Byeon

IPC: H10B43/40 ,  G11C7/18 ,  G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/46 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/40 ,  G11C7/18 ,  G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/46 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: Disclosed is a three-dimensional semiconductor device comprising channel regions that penetrate the stack structure and extend in a direction perpendicular to a top surface of the first substrate, a first interlayer dielectric layer on the stack structure, and a peripheral circuit structure on the first interlayer dielectric layer. The peripheral circuit structure includes peripheral circuit elements on a first surface of a second substrate. The peripheral circuit elements are electrically connected to the channel regions and at least one of the gate electrodes. The first substrate has a first crystal plane parallel to the top surface thereof. The second substrate has a second crystal plane parallel to the first surface thereof. An arrangement direction of atoms of the first crystal plane intersects an arrangement direction of atoms of the second crystal plane.

公开(公告)号：US12089408B2

公开(公告)日：2024-09-10

申请号：US17697386

申请日：2022-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bongsoon Lim ,  Hyunggon Kim

IPC: G11C16/04 ,  G11C16/06 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/27 ,  G11C16/0483 ,  G11C16/06 ,  H10B43/40

Abstract: A non-volatile memory device including a memory cell region over a peripheral circuit region. The memory cell region includes an upper substrate, channel structures extending in a vertical direction, and a first upper metal line extending in a first direction. The peripheral circuit region includes a first lower metal line extending in a second direction, and first and second via structures on the first lower metal line, a top surface of the second via structure in contact with the upper substrate. The memory cell region includes a first through-hole via structure passing through the upper substrate and the first via structure, and electrically connecting the first upper metal line to the first lower metal line; and the first upper metal line is electrically connected to the upper substrate through the first through-hole via structure, the first lower metal line, and the second via structure.

公开(公告)号：US20240069751A1

公开(公告)日：2024-02-29

申请号：US18314978

申请日：2023-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heeseok Eun ,  Jinwook Lee ,  Bongsoon Lim

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/064 ,  G06F3/0679

Abstract: A method is provided to operate a storage device including a storage controller and a plurality of nonvolatile memory devices. A plurality of original data blocks are received at the storage controller from a host. An original parity block is generated based on the original data blocks. The original data blocks and the original parity block are stored in respective ones of the nonvolatile memory devices, wherein a first original data block of the original data blocks is stored in a first one of the nonvolatile memory devices, and wherein the original parity block is stored in a second one of the nonvolatile memory devices. A new data block corresponding to the first original data block is received at the storage controller from the host after storing the original data blocks and the original parity block. The new data block is stored in the first nonvolatile memory device. A new parity block is generated at the second nonvolatile memory device based on the original parity block and based on differences between the first original data block and the new data block.

公开(公告)号：US11854982B2

公开(公告)日：2023-12-26

申请号：US17982255

申请日：2022-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bongsoon Lim ,  Sang-Wan Nam ,  Sang-Won Park ,  Sang-Won Shim ,  Hongsoo Jeon ,  Yonghyuk Choi

IPC: H01L23/535 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L23/535 ,  H10B43/40

Abstract: A three-dimensional semiconductor memory device may include a first stack structure block including first stack structures arranged in a first direction on a substrate, a second stack structure block including second stack structures arranged in the first direction on the substrate, a separation structure disposed on the substrate between the first and second stack structure blocks and including first mold layers and second mold layers, and a contact plug penetrating the separation structure. A bottom surface of the contact plug may contact the substrate.

公开(公告)号：US11829645B2

公开(公告)日：2023-11-28

申请号：US17665926

申请日：2022-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeduk Yu ,  Bongsoon Lim ,  Yonghyuk Choi

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0652 ,  G06F3/0653 ,  G06F3/0679

Abstract: A memory device, a memory system, and/or a method of operating a memory system includes measuring, using processing circuitry, an erase program interval (EPI) of a memory group included in a non-volatile memory (NVM), the EPI being a time period from an erase time point to a program time point of the memory group, determining, using the processing circuitry, a plurality of program modes based on a number of data bits stored in each memory cell of the memory group, selecting, using the processing circuitry, a program mode for the memory group from the plurality of program modes, based on the measured EPI of the memory group, and performing, using the processing circuitry, a program operation on the memory group corresponding to the selected program mode.

公开(公告)号：US20230162791A1

公开(公告)日：2023-05-25

申请号：US17825764

申请日：2022-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongsoo Jeon ,  Bongsoon Lim ,  Sangwan Nam

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/20 ,  G11C5/06

CPC classification number: G11C16/0433 ,  G11C16/08 ,  G11C16/20 ,  G11C5/063

Abstract: A nonvolatile memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes word-lines, at least one string selection line, at least one ground selection line, and a memory cell array including at least one memory block. The second semiconductor includes a first address decoder and a second address decoder. The first address decoder is disposed under a first extension region adjacent to a first side of a cell region and includes a plurality of first pass transistors driving the word-lines, the at least one string selection line, and the at least one ground selection line. The second address decoder is disposed under a second extension region adjacent to a second side of the cell region and includes a plurality of second pass transistors driving the at least one string selection line and the at least one ground selection line.

公开(公告)号：US11581297B2

公开(公告)日：2023-02-14

申请号：US17026637

申请日：2020-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk Choi ,  Bongsoon Lim ,  Hongsoo Jeon ,  Jaeduk Yu

IPC: H01L23/528 ,  H01L23/522 ,  H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  G11C16/08 ,  G11C16/04

Abstract: A memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines and bitlines, an upper substrate, and a memory cell array. The memory cell array includes a memory blocks. The second semiconductor layer includes a lower substrate, and an address decoder. Each memory block includes a core region including a memory cells, a first extension region adjacent to a first side of the core region and including a plurality of wordline contacts, and a second extension region adjacent to a second side of the core region and including an insulating mold structure. The second extension region includes step zones and at least one flat zone. Through-hole vias penetrating the insulating mold structure are in the flat zone. The wordlines and the address decoder are electrically connected with each other by at least the through-hole vias.