公开(公告)号：US20180240808A1

公开(公告)日：2018-08-23

申请号：US15714254

申请日：2017-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minyeong SONG ,  Chadong Yeo ,  Jaeduk Lee ,  Jaehoon Jang

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  G11C16/12

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  H01L27/11565 ,  H01L27/1157

Abstract: A three-dimensional (3D) semiconductor memory device includes an electrode structure including a plurality of cell electrodes vertically stacked on a substrate and extending in a first direction, lower and upper string selection electrodes sequentially stacked on the electrode structure, a first vertical structure penetrating the lower and upper string selection electrodes and the electrode structure, a second vertical structure spaced apart from the upper string selection electrode and penetrating the lower string selection electrode and the electrode structure, and a first bit line intersecting the electrode structure and extending in a second direction different from the first direction. The first bit line is connected in common to the first and second vertical structures. The second vertical structure does not extend through the upper string selection electrode.

公开(公告)号：US09515087B2

公开(公告)日：2016-12-06

申请号：US14878453

申请日：2015-10-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunghwan Son ,  Jaesung Sim ,  Shinhwan Kang ,  Youngwoo Park ,  Jaeduk Lee

IPC: G11C5/02 ,  H01L27/115 ,  G11C16/30 ,  H01L29/34 ,  G11C16/04

CPC classification number: H01L27/11575 ,  G11C5/025 ,  G11C16/0483 ,  G11C16/30 ,  H01L27/11517 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/34

Abstract: A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure. At least one of the memory blocks includes a well plate electrode, a semiconductor layer in contact with a first surface of the well plate electrode, a stack structure including a plurality of electrodes vertically stacked on the semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to the semiconductor layer.

Abstract translation: 一种三维（3D）半导体存储器件，其包括外围逻辑结构，该外围逻辑结构包括设置在半导体衬底上的外围逻辑电路和与外围逻辑电路重叠的第一绝缘层，以及在周边彼此间隔开的多个存储块 逻辑结构。 存储块中的至少一个包括阱板电极，与阱板电极的第一表面接触的半导体层，包括垂直堆叠在半导体层上的多个电极的堆叠结构，以及穿透 堆叠结构并连接到半导体层。

公开(公告)号：US20250062229A1

公开(公告)日：2025-02-20

申请号：US18660743

申请日：2024-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changhee Lee ,  Chulmin Choi ,  Sangyong Park ,  Dajin Kim ,  Taeho Kim ,  Gunwook Yoon ,  Taehun Kim ,  Seungjae Baik ,  Jaeduk Lee

IPC: H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device includes a first semiconductor structure that includes a first substrate, circuit devices on the first substrate, a lower interconnection structure, and a lower bonding structure; and a second semiconductor structure disposed on and connected to the first semiconductor structure The second semiconductor structure includes a stack structure; channel structures that including a first portion that penetrate through the stack structure in the vertical direction and a second portion that extends upward from the first portion; a first material layer disposed on the stack structure and the channel structure and having first conductivity; and a second material layer disposed between the first material layer and the stack structure and having second conductivity., The first material layer overlaps second portions of the channel structures in the vertical direction, and the second material layer does not overlap the second portions of the channel structures in the vertical direction.

公开(公告)号：US12080799B2

公开(公告)日：2024-09-03

申请号：US17715887

申请日：2022-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sohyeon Lee ,  Sungsu Moon ,  Jaeduk Lee ,  Ikhyung Joo

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/78603 ,  H01L29/0607

Abstract: A semiconductor device includes a substrate having a recess therein that is partially filled with at least two semiconductor active regions. The recess has sidewalls and a bottom that are sufficiently lined with corresponding substrate insulating layers that the at least two semiconductor active regions are electrically isolated from the substrate, which surrounds the sidewalls and bottom of the recess. A sidewall insulating layer is provided, which extends as a partition between first and second ones of the at least two semiconductor active regions, such that the first and second ones of the at least two semiconductor active regions are electrically isolated from each other. First and second gate electrodes are provided in the first and second active regions, respectively.

公开(公告)号：US11916078B2

公开(公告)日：2024-02-27

申请号：US17854128

申请日：2022-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sohyeon Lee ,  Sungsu Moon ,  Jaeduk Lee ,  Ikhyung Joo

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/1207 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/823487 ,  H01L21/84 ,  H01L27/0886 ,  H01L29/0843 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/4236 ,  H01L29/42392 ,  H01L29/7831 ,  H01L29/785 ,  H01L29/78642 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate having an active region defined by a device isolation film and providing a first channel region; a first source/drain region in the active region on first and second sides of the first channel region; a gate structure having a first gate insulating film, a shared gate electrode, and a second gate insulating film, sequentially arranged on the active region; a cover semiconductor layer on the second gate insulating film and electrically separated from the active region to provide a second channel region; a second source/drain region in the cover semiconductor layer on first and second sides of the second channel region; first and second source/drain contacts respectively connected to the first and second source/drain regions; and a shared gate contact connected to the shared gate electrode.

公开(公告)号：US20220376116A1

公开(公告)日：2022-11-24

申请号：US17715887

申请日：2022-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sohyeon Lee ,  Sungsu Moon ,  Jaeduk Lee ,  Ikhyung Joo

IPC: H01L29/786 ,  H01L29/06

Abstract: A semiconductor device includes a substrate having a recess therein that is partially filled with at least two semiconductor active regions. The recess has sidewalls and a bottom that are sufficiently lined with corresponding substrate insulating layers that the at least two semiconductor active regions are electrically isolated from the substrate, which surrounds the sidewalls and bottom of the recess. A sidewall insulating layer is provided, which extends as a partition between first and second ones of the at least two semiconductor active regions, such that the first and second ones of the at least two semiconductor active regions are electrically isolated from each other. First and second gate electrodes are provided in the first and second active regions, respectively.

公开(公告)号：US20220336501A1

公开(公告)日：2022-10-20

申请号：US17854128

申请日：2022-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sohyeon Lee ,  Sungsu Moon ,  Jaeduk Lee ,  Ikhyung Joo

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/08 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate having an active region defined by a device isolation film and providing a first channel region; a first source/drain region in the active region on first and second sides of the first channel region; a gate structure having a first gate insulating film, a shared gate electrode, and a second gate insulating film, sequentially arranged on the active region; a cover semiconductor layer on the second gate insulating film and electrically separated from the active region to provide a second channel region; a second source/drain region in the cover semiconductor layer on first and second sides of the second channel region; first and second source/drain contacts respectively connected to the first and second source/drain regions; and a shared gate contact connected to the shared gate electrode.

公开(公告)号：US11444094B2

公开(公告)日：2022-09-13

申请号：US16782737

申请日：2020-02-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sejun Park ,  Jaeduk Lee ,  Jaehoon Jang ,  Jin-Kyu Kang ,  Seungwan Hong ,  Okcheon Hong

IPC: H01L27/11582 ,  H01L27/11556 ,  G11C5/02

Abstract: A semiconductor memory device includes a stack structure including electrodes and insulating layers alternately stacked on a substrate, and a vertical channel structure penetrating the stack structure. The vertical channel structure includes a semiconductor pattern and a vertical insulating layer between the semiconductor pattern and the electrodes. The vertical insulating layer includes a charge storage layer, a filling insulating layer, and a tunnel insulating layer. The vertical insulating layer has a cell region between the semiconductor pattern and each electrode and a cell separation region between the semiconductor pattern and each insulating layer. A portion of the charge storage layer of the cell region is in physical contact with the tunnel insulating layer. The filling insulating layer is between the semiconductor pattern and a remaining portion of the charge storage layer of the cell region.

公开(公告)号：US11380706B2

公开(公告)日：2022-07-05

申请号：US16936888

申请日：2020-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangyong Park ,  Hyunseok Na ,  Jaeduk Lee

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

Abstract: An integrated circuit device includes a plurality of conductive lines extending in a horizontal direction parallel to a main surface of a substrate and overlapping one another in a vertical direction vertical to the main surface, on the substrate, a plurality of insulation layers each between two adjacent conductive lines of the plurality of conductive lines to extend in the horizontal direction, a channel layer extending in the vertical direction in a channel hole passing through the plurality of conductive lines and the plurality of insulation layers, and a plurality of outer blocking dielectric layers between the plurality of conductive lines and the channel layer, in at least some of the plurality of conductive lines, wherein a width of each of the plurality of outer blocking dielectric layers in the horizontal direction increases toward the main surface.

公开(公告)号：US10396088B2

公开(公告)日：2019-08-27

申请号：US15696276

申请日：2017-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sohyeon Lee ,  Sunil Shim ,  Jaeduk Lee ,  Jaehoon Jang ,  Jeehoon Han

IPC: H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/52 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

Abstract: A three-dimensional semiconductor device and a method of manufacturing the same are provided. The three-dimensional semiconductor device includes a stack structure including insulating layers and electrodes that are alternately stacked on a substrate, a horizontal semiconductor pattern between the substrate and the stack structure, vertical semiconductor patterns penetrating the stack structure and connected to the horizontal semiconductor pattern; and a common source plug at a side of the stack structure. The stack structure, the horizontal semiconductor pattern and the common source plug extend in a first direction. The horizontal semiconductor pattern includes a first sidewall extending in the first direction. The first sidewall has protrusions protruding toward the common source plug.