公开(公告)号：US11894079B2

公开(公告)日：2024-02-06

申请号：US17384219

申请日：2021-07-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeji Lee ,  Raeyoung Lee ,  Jinkyu Kang ,  Sejun Park ,  Jaeduk Lee

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C16/3463 ,  G11C16/102 ,  G11C16/26 ,  G11C16/3404

Abstract: A memory controller includes an over-program controller that preprograms and then erases the memory cells such that each of the memory cells has a first threshold voltage level, wherein fast cells are detected among the memory cells according to a threshold voltage less than or equal to a second threshold voltage less than the first threshold voltage, and a processor that generates fast cell information identifying the fast cells among the memory cells and stores the fast cell information in a buffer. The over-program controller controls the over-programming of the fast cells and normal programming of normal cells among the memory cells based on the fast cell information stored in the buffer.

公开(公告)号：US20200303390A1

公开(公告)日：2020-09-24

申请号：US16782737

申请日：2020-02-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sejun Park ,  Jaeduk Lee ,  Jaehoon Jang ,  Jin-Kyu Kang ,  Seungwan Hong ,  Okcheon Hong

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/02

Abstract: A semiconductor memory device includes a stack structure including electrodes and insulating layers alternately stacked on a substrate, and a vertical channel structure penetrating the stack structure. The vertical channel structure includes a semiconductor pattern and a vertical insulating layer between the semiconductor pattern and the electrodes. The vertical insulating layer includes a charge storage layer, a filling insulating layer, and a tunnel insulating layer. The vertical insulating layer has a cell region between the semiconductor pattern and each electrode and a cell separation region between the semiconductor pattern and each insulating layer. A portion of the charge storage layer of the cell region is in physical contact with the tunnel insulating layer. The filling insulating layer is between the semiconductor pattern and a remaining portion of the charge storage layer of the cell region.

公开(公告)号：US10396093B2

公开(公告)日：2019-08-27

申请号：US15714254

申请日：2017-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minyeong Song ,  Chadong Yeo ,  Jaeduk Lee ,  Jaehoon Jang

IPC: H01L27/11582 ,  H01L27/11565 ,  G11C16/12 ,  H01L27/1157 ,  G11C16/04 ,  G11C16/10

Abstract: A three-dimensional (3D) semiconductor memory device includes an electrode structure including a plurality of cell electrodes vertically stacked on a substrate and extending in a first direction, lower and upper string selection electrodes sequentially stacked on the electrode structure, a first vertical structure penetrating the lower and upper string selection electrodes and the electrode structure, a second vertical structure spaced apart from the upper string selection electrode and penetrating the lower string selection electrode and the electrode structure, and a first bit line intersecting the electrode structure and extending in a second direction different from the first direction. The first bit line is connected in common to the first and second vertical structures. The second vertical structure does not extend through the upper string selection electrode.

公开(公告)号：US10332902B2

公开(公告)日：2019-06-25

申请号：US15805513

申请日：2017-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunghwan Son ,  Jaesung Sim ,  Shinhwan Kang ,  Youngwoo Park ,  Jaeduk Lee

IPC: H01L27/11575 ,  H01L27/11582 ,  H01L27/11573 ,  H01L29/34 ,  H01L27/11526 ,  G11C5/02 ,  G11C16/04 ,  H01L27/11517 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11548 ,  H01L27/11556 ,  G11C16/30 ,  H01L27/11551

Abstract: A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure. At least one of the memory blocks includes a well plate electrode, a semiconductor layer in contact with a first surface of the well plate electrode, a stack structure including a plurality of electrodes vertically stacked on the semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to the semiconductor layer.

公开(公告)号：US10032789B2

公开(公告)日：2018-07-24

申请号：US15208669

申请日：2016-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohyun Lee ,  Younghwan Son ,  Minyeong Song ,  Youngwoo Park ,  Jaeduk Lee

IPC: H01L27/115 ,  H01L29/167 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  H01L27/11582 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573

Abstract: Provided is a three-dimensional semiconductor memory device including a peripheral logic structure on a semiconductor substrate to include peripheral logic circuits and a lower insulating gapfill layer, a horizontal semiconductor layer on the peripheral logic structure, stacks on the horizontal semiconductor layer, each of the stacks including a plurality of electrodes vertically stacked on the horizontal semiconductor layer, and a plurality of vertical structures passing through the stacks and connected to the horizontal semiconductor layer. The horizontal semiconductor layer may include a first semiconductor layer disposed on the lower insulating gapfill layer and co-doped with an anti-diffusion material and first conductivity type impurities of a first impurity concentration, and a second semiconductor layer disposed on the first semiconductor layer and doped with first conductivity type impurities of a second impurity concentration lower than the first impurity concentration or undoped.

公开(公告)号：US10002877B2

公开(公告)日：2018-06-19

申请号：US15448697

申请日：2017-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jintaek Park ,  Youngwoo Park ,  Jaeduk Lee

IPC: G11C5/02 ,  H01L27/11573 ,  G11C16/04 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/1157

CPC classification number: H01L27/11573 ,  G11C5/02 ,  G11C5/025 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: A three-dimensional (3D) semiconductor memory device includes a CMOS circuit structure including a plurality of column blocks each comprising a plurality of page buffer circuits, and a lower wiring structure and a memory structure sequentially stacked over the CMOS circuit structure. The memory structure overlaps a first circuit region of the CMOS circuit structure and does not overlap a second circuit region of the CMOS circuit structure, and the plurality of column blocks are contained within the first circuit region of the CMOS circuit structure.

公开(公告)号：US20250040176A1

公开(公告)日：2025-01-30

申请号：US18629093

申请日：2024-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngtaek Oh ,  Jiwoong Kim ,  Taehun Kim ,  Minkyung Bae ,  Seungjae Baik ,  Jaeduk Lee ,  Doohee Hwang

IPC: H01L29/78 ,  H01L23/00 ,  H01L25/065 ,  H01L29/08 ,  H01L29/10 ,  H10B80/00

Abstract: A semiconductor device includes a peripheral circuit structure and a cell structure stacked on the peripheral circuit structure. The cell structure includes a plurality of gate electrodes spaced apart from each other in a vertical direction, a channel structure passing through the plurality of gate electrodes and extending in the vertical direction, the channel structure having a first end close to the peripheral circuit structure and a second end opposite to the first end, and a common source layer covering the second end of the channel structure. The channel structure includes a channel layer extending in the vertical direction, the common source layer includes a first region and a second region that contain impurities of different conductivity types, and the first region of the common source layer is connected to at least a portion of the channel layer.

公开(公告)号：US12131781B2

公开(公告)日：2024-10-29

申请号：US17689005

申请日：2022-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeduk Lee ,  Kinam Kim ,  Sujin Ahn

IPC: G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: Provided are semiconductor devices and data storage systems including the same. The semiconductor devices may include first and second separation structures parallel to each other, a block between the first and second separation structures, and bit lines on the block. The block includes strings, the bit lines include a first bit line electrically connected to first and second strings, each of the strings includes a lower select transistor, memory cell transistors, and upper select transistors connected in series, the upper select transistors in each of the strings include a first upper select transistor and a second upper select transistor below the first upper select transistor. The first upper select transistors of the first and second strings may share a single first upper select gate electrode. Gate electrodes of the lower select transistors of the first and second strings may include surfaces coplanar with each other.

公开(公告)号：US20240206177A1

公开(公告)日：2024-06-20

申请号：US18591076

申请日：2024-02-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wukang Kim ,  Sejun Park ,  Hyoje Bang ,  Jaeduk Lee ,  Junghoon Lee

IPC: H10B43/27 ,  H01L23/522 ,  H01L23/535 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/535 ,  H10B43/35

Abstract: A semiconductor device including a stack structure including gate layers and interlayer insulating layers spaced apart in a vertical direction, a channel hole penetrating the stack structure in the vertical direction, a core region extending within the channel hole, a channel layer disposed on a side surface of the core region, a first dielectric layer, a data storage layer and a second dielectric layer, which are disposed between the channel layer and the gate layers, and a pad pattern disposed on the core region, in the channel hole, and in contact with the channel layer. A first horizontal distance between a side surface of a first portion of an uppermost gate layer and an outer side surface of the channel layer is greater than a second horizontal distance between a side surface of a second portion of the uppermost gate layer and an outer side surface of the pad pattern.

公开(公告)号：US11974434B2

公开(公告)日：2024-04-30

申请号：US17824821

申请日：2022-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangyong Park ,  Hyunseok Na ,  Jaeduk Lee

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/10 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/10 ,  H10B43/10

Abstract: An integrated circuit device includes a plurality of conductive lines extending in a horizontal direction parallel to a main surface of a substrate and overlapping one another in a vertical direction vertical to the main surface, on the substrate, a plurality of insulation layers each between two adjacent conductive lines of the plurality of conductive lines to extend in the horizontal direction, a channel layer extending in the vertical direction in a channel hole passing through the plurality of conductive lines and the plurality of insulation layers, and a plurality of outer blocking dielectric layers between the plurality of conductive lines and the channel layer, in at least some of the plurality of conductive lines, wherein a width of each of the plurality of outer blocking dielectric layers in the horizontal direction increases toward the main surface.