公开(公告)号：US20150380450A1

公开(公告)日：2015-12-31

申请号：US14746926

申请日：2015-06-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki OKAMOTO ,  Yoshiyuki KUROKAWA ,  Hiroki INOUE ,  Takuro OHMARU

IPC: H01L27/146 ,  H01L31/105 ,  H01L31/0272 ,  H01L29/786

CPC classification number: H01L27/14616 ,  H01L27/14603 ,  H01L27/14621 ,  H01L27/14641 ,  H01L27/14643 ,  H01L29/7869 ,  H01L31/0272 ,  H01L31/105

Abstract: An imaging device with high productivity and improved dynamic range is provided. The imaging device includes a pixel driver circuit and a photoelectric conversion element including a p-type semiconductor, an n-type semiconductor, and an i-type semiconductor. In a plan view, the total area of a part of the i-type semiconductor overlapped with neither a metal material nor a semiconductor material constituting the pixel driver circuit is preferably greater than or equal to 65%, more preferably greater than or equal to 80%, and still more preferably greater than or equal to 90% of the area of the whole i-type semiconductor. Plural photoelectric conversion elements are provided in the same semiconductor, whereby a process for separating the photoelectric conversion elements can be omitted. The i-type semiconductors in the plural photoelectric conversion elements are separated from each other by the p-type semiconductor or the n-type semiconductor.

Abstract translation: 提供了具有高生产率和改进的动态范围的成像装置。 该成像装置包括像素驱动电路和包括p型半导体，n型半导体和i型半导体的光电转换元件。 在平面图中，与构成像素驱动电路的金属材料和半导体材料不重叠的i型半导体的一部分的总面积优选为65％以上，更优选为80以上 ％，还更优选大于或等于整个i型半导体的面积的90％。 多个光电转换元件设置在相同的半导体中，由此可以省略用于分离光电转换元件的处理。 多个光电转换元件中的i型半导体通过p型半导体或n型半导体彼此分离。

公开(公告)号：US20150256182A1

公开(公告)日：2015-09-10

申请号：US14635257

申请日：2015-03-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki OKAMOTO ,  Yoshiyuki KUROKAWA

IPC: H03K19/177

CPC classification number: H03K19/1776

Abstract: Provided is a semiconductor device where a signal-transmission speed. The semiconductor device comprises a first logic element, a first switch electrically connected to the first logic element, and a second logic element electrically connected to the first switch. The first logic element includes at least a second switch, and the second switch has a function of setting an output potential from the first logic element to a L level. The first logic element may include a memory electrically connected to a register. The memory has a function of holding data of the register, and the register has a function of setting an output potential to a L level after holding the data in the memory.

Abstract translation: 提供了一种信号传输速度的半导体器件。 半导体器件包括第一逻辑元件，电连接到第一逻辑元件的第一开关和与第一开关电连接的第二逻辑元件。 第一逻辑元件包括至少第二开关，并且第二开关具有将来自第一逻辑元件的输出电位设置为L电平的功能。 第一逻辑元件可以包括电连接到寄存器的存储器。 存储器具有保持寄存器的数据的功能，并且该寄存器具有在将数据保存在存储器中之后将输出电位设置为L电平的功能。

公开(公告)号：US20240373709A1

公开(公告)日：2024-11-07

申请号：US18688811

申请日：2022-08-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki OKAMOTO ,  Tatsuya ONUKI ,  Hidetomo KOBAYASHI ,  Takanori MATSUZAKI ,  Munehiro KOZUMA

IPC: H10K59/131 ,  H01L27/12 ,  H10K50/19 ,  H10K59/121

Abstract: An object is to provide a semiconductor device in which the number of control wirings is reduced. In a semiconductor device of one embodiment of the present invention, a first wiring (GLa) is connected to a first input terminal (54a) of a logic circuit (54) and a gate of a sixth transistor (M6); a second wiring (GLb) is connected to a second input terminal (54b) of the logic circuit (54), a gate of the third transistor (M3), a gate of the fourth transistor (M4), and a gate of the fifth transistor (M5); a gate of the first transistor (M1) is connected to an output terminal (54y) of the logic circuit (54); and the logic circuit (54) has a function of outputting a signal obtained by a logic operation of a signal input to the first input terminal (54a) and a signal input to the second input terminal (54b) to the output terminal (54y).

公开(公告)号：US20240029773A1

公开(公告)日：2024-01-25

申请号：US18245784

申请日：2021-09-09

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yuki OKAMOTO ,  Tatsuya ONUKI ,  Takanori MATSUZAKI

IPC: G11C11/22

CPC classification number: G11C11/2257 ,  G11C11/2273 ,  G11C11/2293

Abstract: A semiconductor device with high reliability is provided. The semiconductor device includes a memory cell including a first ferroelectric capacitor and a reference memory cell including a second ferroelectric capacitor. In a first period, first binary data is written to the memory cell, and first reference binary data is written to the reference memory cell. In a second period, the first binary data is read from the memory cell, and the first reference binary data is read from the reference memory cell. In a third period, logic operation of the first binary data and the first reference binary data is performed. In a fourth period, second binary data is written to the memory cell, and second reference binary data is written to the reference memory cell. A value of the first binary data and a value of the second binary data are different from each other, and a value of the first reference binary data and a value of the second reference binary data are different from each other.

公开(公告)号：US20230352477A1

公开(公告)日：2023-11-02

申请号：US18016880

申请日：2021-07-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takanori MATSUZAKI ,  Tatsuya ONUKI ,  Munehiro KOZUMA ,  Takeshi AOKI ,  Yuki OKAMOTO ,  Takayuki IKEDA

IPC: H01L27/06 ,  H01L29/786 ,  G06F7/544 ,  H01L27/092 ,  G06N3/065

CPC classification number: H01L27/0688 ,  H01L29/7869 ,  G06F7/5443 ,  H01L29/78618 ,  H01L29/78696 ,  H01L27/0924 ,  G06N3/065

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a digital calculator, an analog calculator, a first memory circuit, and a second memory circuit. The analog calculator, the first memory circuit, and the second memory circuit each include a transistor including an oxide semiconductor in a channel formation region. The first memory circuit has a function of supplying first weight data to the digital calculator as digital data. The digital calculator has a function of performing product-sum operation using the first weight data. The second memory circuit has a function of supplying second weight data to the analog calculator as analog data. The analog calculator has a function of performing product-sum operation using the second weight data. The amount of current flowing between a source and a drain of at least one of the transistors each including the oxide semiconductor in the channel formation region in the analog calculator and the second memory circuit is the amount of current flowing when the transistor operates in a subthreshold region.

公开(公告)号：US20230099168A1

公开(公告)日：2023-03-30

申请号：US17802281

申请日：2021-03-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki OKAMOTO ,  Tatsuya ONUKI ,  Munehiro KOZUMA ,  Takanori MATSUZAKI

IPC: G11C7/10 ,  G11C7/12 ,  G11C8/08 ,  H10B12/00 ,  H01L29/786

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a plurality of arithmetic blocks each including an arithmetic circuit portion and a memory circuit portion. The arithmetic circuit portion and the memory circuit portion are electrically connected to each other. The arithmetic circuit portion and the memory circuit portion have an overlap region. The arithmetic circuit portion includes, for example, a Si transistor, and the memory circuit portion includes, for example, an OS transistor. The arithmetic circuit portion has a function of performing product-sum operation. The memory circuit portion has a function of retaining weight data. A first driver circuit has a function of writing the weight data to the memory circuit portion. The weight data is written to all the memory circuit portions included in the same column with the use of the first driver circuit.

公开(公告)号：US20230066071A1

公开(公告)日：2023-03-02

申请号：US17894261

申请日：2022-08-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yusuke KOUMURA ,  Yuki OKAMOTO ,  Toshiki MIZUGUCHI ,  Tatsuya ONUKI ,  Hideki UOCHI

IPC: G09G3/20 ,  G09G3/3233

Abstract: A novel image correction system is provided. The image correction system includes an imaging device, a first arithmetic device, a display portion including a plurality of pixels, and a second arithmetic device. The imaging device obtains imaging data by capturing a first-gray-level image displayed on the display portion. The first arithmetic device calculates the luminous intensity of each of the pixels and a correction standard by using the imaging data. The first arithmetic device calculates correction data for each of the pixels by using the luminous intensity and the correction standard. The second arithmetic device corrects a video signal by using the correction data. The display portion displays an image using the corrected video signal. The first arithmetic device calculates correction data for pixels that emit red light, pixels that emit green light, and pixels that emit blue light and modifies the correction data by using color temperature data.

公开(公告)号：US20220415941A1

公开(公告)日：2022-12-29

申请号：US17781152

申请日：2020-12-14

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Seiichi YONEDA ,  Toshiki HAMADA ,  Yuki OKAMOTO ,  Shunpei YAMAZAKI

IPC: H01L27/146 ,  H04N5/378 ,  H04N5/3745

Abstract: An imaging device with an arithmetic function in which the circuit size is reduced is provided. The imaging device includes a plurality of pixel blocks. Each of the pixel blocks includes N (N is an integer greater than or equal to 1) first circuits, N second circuits, and a third circuit. Each of the first circuits includes a photoelectric conversion device, and the photoelectric conversion device has a function of converting incident light into an electrical signal and has a function of outputting a first signal that is obtained by binarizing the electrical signal to the second circuit. Each of the second circuits has a function of outputting a second signal that is obtained by multiplying the first signal by a weight coefficient to a third circuit. When the N second signals are output to a wiring electrically connected to the third circuit, addition is performed. The first circuit includes a transistor, and an OS transistor is preferably used as the transistor.

公开(公告)号：US20220392521A1

公开(公告)日：2022-12-08

申请号：US17890335

申请日：2022-08-18

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yuki OKAMOTO ,  Tatsuya ONUKI

IPC: G11C11/4097 ,  G11C11/4091 ,  H01L27/105 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786

Abstract: A novel memory device is provided. A first cell array including a plurality of memory cells and a second cell array including a plurality of memory cells are provided to overlap with each other. Two bit lines included in the first bit line pair are electrically connected to part of the memory cells included in the first cell array and to part of the memory cells included in the second cell array. Two bit lines included in the second bit line pair are electrically connected to part of the memory cells included in the first cell array and to part of the memory cells included in the second cell array. In the first cell array, one of the bit lines included in the second bit line pair includes a region overlapping with part of the first bit line pair. In the second cell array, the other of the bit lines included in the second bit line pair includes a region overlapping with part of the first bit line pair.

公开(公告)号：US20220262858A1

公开(公告)日：2022-08-18

申请号：US17629804

申请日：2020-07-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hajime KIMURA ,  Takanori MATSUZAKI ,  Tatsuya ONUKI ,  Yuki OKAMOTO ,  Hideki UOCHI ,  Satoru OKAMOTO ,  Hiromichi GODO ,  Kazuki TSUDA ,  Hitoshi KUNITAKE

IPC: H01L27/24

Abstract: A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. A first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween are provided in the first conductor. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.