公开(公告)号：US09680061B2

公开(公告)日：2017-06-13

申请号：US15212659

申请日：2016-07-18

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur

IPC: H01L27/15 ,  H01L31/072 ,  H01L33/22 ,  H01L33/12 ,  H01L33/32 ,  H01L21/02 ,  H01L29/66 ,  H01L29/20 ,  H01L29/34 ,  H01L29/778 ,  H01L33/24 ,  H01L29/205 ,  H01L33/00 ,  H01L33/06 ,  H01L33/10

CPC classification number: H01L33/22 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/02658 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/34 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L33/007 ,  H01L33/06 ,  H01L33/10 ,  H01L33/12 ,  H01L33/24 ,  H01L33/32 ,  H01L2933/0091

Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.

公开(公告)号：US20170110628A1

公开(公告)日：2017-04-20

申请号：US15391994

申请日：2016-12-28

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Jinwei Yang ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/12 ,  H01L33/32 ,  H01L33/06 ,  C30B29/40 ,  H01L33/62 ,  H01L33/46 ,  H01L33/00 ,  H01L33/14 ,  H01L33/40

CPC classification number: H01L33/12 ,  C30B29/403 ,  G06F17/505 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/06 ,  H01L33/145 ,  H01L33/32 ,  H01L33/405 ,  H01L33/46

Abstract: A semiconductor structure comprising a buffer structure and a set of semiconductor layers formed adjacent to a first side of the buffer structure is provided. The buffer structure can have an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa. The buffer structure can be grown using a set of growth parameters selected to achieve the target effective lattice constant a, control stresses present during growth of the buffer structure, and/or control stresses present after the semiconductor structure has cooled.

公开(公告)号：US20170098739A1

公开(公告)日：2017-04-06

申请号：US15283462

申请日：2016-10-03

Applicant: Sensor Electronic Technology, Inc.

Inventor： Mikhail Gaevski ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur

IPC: H01L33/38 ,  H01L33/32 ,  H01L33/12 ,  H01L33/00 ,  H01L31/0232 ,  H01L31/109 ,  H01L31/0304 ,  H01L31/0352 ,  H01L31/0392 ,  H01L31/0224 ,  H01L31/18 ,  H01S5/22 ,  H01S5/042 ,  H01S5/343 ,  H01L33/40

CPC classification number: H01L33/387 ,  H01L31/022408 ,  H01L31/02327 ,  H01L31/03048 ,  H01L31/035236 ,  H01L31/0392 ,  H01L31/109 ,  H01L31/1848 ,  H01L31/1852 ,  H01L33/007 ,  H01L33/12 ,  H01L33/20 ,  H01L33/32 ,  H01L33/38 ,  H01L33/405 ,  H01L33/46 ,  H01L2933/0016 ,  H01L2933/0091 ,  Y02E10/50

Abstract: An optoelectronic device with a multi-layer contact is described. The optoelectronic device can include a n-type semiconductor layer having a surface. A mesa can be located over a first portion of the surface of the n-type semiconductor layer and have a mesa boundary. A n-type contact region can be located over a second portion of the surface of the n-type semiconductor contact layer entirely distinct from the first portion, and be at least partially defined by the mesa boundary. A first n-type metallic contact layer can be located over at least a portion of the n-type contact region in proximity of the mesa boundary, where the first n-type metallic contact layer forms an ohmic contact with the n-type semiconductor layer. A second n-type metallic contact layer can be located over a second portion of the n-type contact region, where the second n-type metallic contact layer is formed of a reflective metallic material.

公开(公告)号：US20170062657A1

公开(公告)日：2017-03-02

申请号：US15149782

申请日：2016-05-09

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/22 ,  G06F17/50 ,  H01L33/20 ,  H01L33/00 ,  H01L33/10

CPC classification number: H01L33/22 ,  F21V5/002 ,  G06F17/5009 ,  G06F17/5045 ,  H01L33/007 ,  H01L33/10 ,  H01L33/20 ,  H01L2933/0058 ,  H01L2933/0083 ,  Y10T29/49

Abstract: A profiled surface for improving the propagation of radiation through an interface is provided. The profiled surface includes a set of large roughness components providing a first variation of the profiled surface having a characteristic scale approximately an order of magnitude larger than a target wavelength of the radiation. The set of large roughness components can include a series of truncated shapes. The profiled surface also includes a set of small roughness components superimposed on the set of large roughness components and providing a second variation of the profiled surface having a characteristic scale on the order of the target wavelength of the radiation.

Abstract translation: 提供了用于改善辐射通过界面的传播的异型表面。 成形表面包括一组大的粗糙度部件，其提供成型表面的第一变化，其特征标度比辐射的目标波长大大大大约一个数量级。 该组粗糙度较大的部件可包括一系列截头形状。 成形表面还包括一​​组小的粗糙度部件，叠加在该组粗糙度较大的部件上，并提供具有辐射目标波长级的特征刻度的成型表面的第二变型。

公开(公告)号：US20160322535A1

公开(公告)日：2016-11-03

申请号：US15212659

申请日：2016-07-18

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Wenhong Sun ,  Jinwei Yang ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/22 ,  H01L33/12 ,  H01L29/20 ,  H01L29/778 ,  H01L29/66 ,  H01L29/205 ,  H01L33/06 ,  H01L33/10 ,  H01L21/02 ,  H01L33/00 ,  H01L33/32 ,  H01L29/34

CPC classification number: H01L33/22 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/02658 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/34 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L33/007 ,  H01L33/06 ,  H01L33/10 ,  H01L33/12 ,  H01L33/24 ,  H01L33/32 ,  H01L2933/0091

Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.

公开(公告)号：US09425353B2

公开(公告)日：2016-08-23

申请号：US14504456

申请日：2014-10-02

Applicant: Sensor Electronic Technology, Inc.

Inventor： Michael Shur ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Remigijus Gaska

IPC: H01L33/36 ,  H01L33/12 ,  H01L33/42 ,  H01L33/40 ,  H01L33/38 ,  H01L33/44 ,  H01L33/32 ,  H01L33/14 ,  H01L33/00

CPC classification number: H01L33/12 ,  H01L33/007 ,  H01L33/145 ,  H01L33/32 ,  H01L33/382 ,  H01L33/387 ,  H01L33/405 ,  H01L33/42 ,  H01L33/44 ,  H01L2933/0016 ,  H01L2933/0083 ,  H01L2933/0091

Abstract: A semiconductor structure including an anodic aluminum oxide layer is described. The anodic aluminum oxide layer can be located between a semiconductor layer and another layer of material. The anodic aluminum oxide layer can include a plurality of pores extending to an adjacent surface of the semiconductor layer. The layer of material can penetrate at least some of the plurality of pores and directly contact the semiconductor layer. In an illustrative embodiment, the layer of material is a conductive material and the anodic aluminum oxide is located at a p-type contact.

Abstract translation: 描述了包括阳极氧化铝层的半导体结构。 阳极氧化铝层可以位于半导体层和另一层材料之间。 阳极氧化铝层可以包括延伸到半导体层的相邻表面的多个孔。 材料层可以穿透多个孔中的至少一些并且直接接触半导体层。 在说明性实施例中，材料层是导电材料，阳极氧化铝位于p型接触处。

公开(公告)号：US20160240739A1

公开(公告)日：2016-08-18

申请号：US15138415

申请日：2016-04-26

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Rakesh Jain ,  Jinwei Yang ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/22 ,  H01L33/06 ,  H01L33/12 ,  G06F17/50 ,  H01L33/00 ,  H01L33/32

CPC classification number: H01L33/22 ,  G06F17/5068 ,  G06F2217/12 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02617 ,  H01L21/02639 ,  H01L21/0265 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/06 ,  H01L33/12 ,  H01L33/32 ,  H01L2224/16225

Abstract: A patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings. Each substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the openings can have a characteristic size between approximately 0.1 micron and five microns. One or more of the substantially flat top surfaces can be patterned based on target radiation.

Abstract translation: 提供了用于改善半导体层的生长的图案化表面，例如III族氮化物基半导体层。 图案化表面可以包括一组基本平坦的顶表面和多个开口。 每个基本上平坦的顶表面可以具有小于约0.5纳米的均方根粗糙度，并且开口可以具有在约0.1微米和5微米之间的特征尺寸。 基本平坦的顶表面中的一个或多个可以基于目标辐射进行图案化。

公开(公告)号：US09385271B2

公开(公告)日：2016-07-05

申请号：US14721082

申请日：2015-05-26

Applicant: Sensor Electronic Technology, Inc.

Inventor： Michael Shur ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Remigijus Gaska ,  Jinwei Yang

IPC: H01L33/06 ,  H01L33/32 ,  B82Y10/00 ,  H01L21/02 ,  H01L29/15 ,  H01L33/00 ,  H01L29/778 ,  H01L29/20

CPC classification number: H01L33/06 ,  B82Y10/00 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L29/15 ,  H01L29/2003 ,  H01L29/778 ,  H01L33/0025 ,  H01L33/32

Abstract: A device including one or more layers with lateral regions configured to facilitate the transmission of radiation through the layer and lateral regions configured to facilitate current flow through the layer is provided. The layer can comprise a short period superlattice, which includes barriers alternating with wells. In this case, the barriers can include both transparent regions, which are configured to reduce an amount of radiation that is absorbed in the layer, and higher conductive regions, which are configured to keep the voltage drop across the layer within a desired range.

公开(公告)号：US20160064601A1

公开(公告)日：2016-03-03

申请号：US14935988

申请日：2015-11-09

Applicant: Sensor Electronic Technology, Inc.

Inventor： Remigijus Gaska ,  Maxim S. Shatalov ,  Michael Shur ,  Alexander Dobrinsky

IPC: H01L33/06 ,  H01L33/14 ,  H01L33/32 ,  H01L33/46 ,  H01L33/38 ,  H01L33/00 ,  H01L33/10

CPC classification number: H01L33/06 ,  G06F17/5068 ,  H01L33/0025 ,  H01L33/0075 ,  H01L33/04 ,  H01L33/10 ,  H01L33/145 ,  H01L33/22 ,  H01L33/32 ,  H01L33/38 ,  H01L33/385 ,  H01L33/405 ,  H01L33/46 ,  H01L2933/0058

Abstract: A method of fabricating a light emitting diode, which includes an n-type contact layer and a light generating structure adjacent to the n-type contact layer, is provided. The light generating structure includes a set of quantum wells. The contact layer and light generating structure can be configured so that a difference between an energy of the n-type contact layer and an electron ground state energy of a quantum well is greater than an energy of a polar optical phonon in a material of the light generating structure. Additionally, the light generating structure can be configured so that its width is comparable to a mean free path for emission of a polar optical phonon by an electron injected into the light generating structure.

公开(公告)号：US20160049551A1

公开(公告)日：2016-02-18

申请号：US14728435

申请日：2015-06-02

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/22 ,  H01L33/00 ,  C30B29/68 ,  C30B29/40 ,  H01L33/06 ,  H01L33/32

CPC classification number: H01L33/22 ,  B82Y20/00 ,  C30B29/403 ,  C30B29/68 ,  H01L33/0079 ,  H01L33/20 ,  H01L2933/0083 ,  H01L2933/0091 ,  H01S5/0224 ,  H01S5/34333

Abstract: An interface including roughness components for improving the propagation of radiation through the interface is provided. The interface includes a first profiled surface of a first layer comprising a set of large roughness components providing a first variation of the first profiled surface having a first characteristic scale and a second profiled surface of a second layer comprising a set of small roughness components providing a second variation of the second profiled surface having a second characteristic scale. The first characteristic scale is approximately an order of magnitude larger than the second characteristic scale. The surfaces can be bonded together using a bonding material, and a filler material also can be present in the interface.