公开(公告)号：US20190087681A1

公开(公告)日：2019-03-21

申请号：US15707695

申请日：2017-09-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anish Reghunath ,  Hetul Sanghvi ,  Michael Lachmayr ,  Mihir Mody

IPC: G06K9/46 ,  G06K9/62

Abstract: Systems and methods for performing Census Transforms that includes an input from an image, with a support window created within the image, and a kernel within the support window. The Census Transform calculations and comparisons are performed within the kernel windows. One disclosed method allows for previously performed comparison to be calculated and compared as an if not equal invert or if equal use pervious comparison hardware design. Alternatively, a new Census Transform is disclosed which always inverts a previously made comparison. This new approach can be demonstrated to be equivalent to, applying the original Census Transform, on a pre-processed input kernel, w here the pre-processing step adds a fractional position index to each pixel within the N×N kernel. The fractional positional index ensures that no two pixels are equal to one another, and thereby makes the Original Census algorithm on pre-processed kernel same as the new Census algorithm on original kernel. The hardware design for this new Census Transform kernel allows for an always invert of previous comparison system resulting in reduced hardware and power consumption.

公开(公告)号：US20160373775A1

公开(公告)日：2016-12-22

申请号：US15257550

申请日：2016-09-06

Applicant: Texas Instruments Incorporated

Inventor： Mihir Mody

IPC: H04N19/436 ,  H04N19/82 ,  H04N19/423 ,  H04N19/174

CPC classification number: H04N19/436 ,  H04N19/119 ,  H04N19/156 ,  H04N19/174 ,  H04N19/423 ,  H04N19/82

Abstract: The disclosure provides a video encoder. The video encoder receives a frame and divides the frame into a plurality of tiles. The video encoder includes a plurality of video processing engines communicatively coupled with each other. Each video processing engine receives a tile of the plurality of tiles. A height of each tile is equal to a height of the frame and each tile comprises a plurality of rows. The plurality of video processing engines includes a first and a second video processing engine. The second video processing engine being initiated after the first video processing engines processes M rows of the plurality of rows of the tile, where M is an integer.

公开(公告)号：US20250147674A1

公开(公告)日：2025-05-08

申请号：US18790153

申请日：2024-07-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sai Rajaraman ,  Mihir Mody ,  William Wallace ,  Niraj Nandan

IPC: G06F3/06

Abstract: Various examples disclosed herein relate to controlling access to non-volatile memory devices. In an example embodiment, a device is provided. The device includes a memory security controller configured to operate in a first functional safety mode or a second functional safety mode, a security mode selection controller coupled to the memory security controller, and a memory interface controller coupled to the memory security controller and the security mode selection controller and configured to couple to a non-volatile memory. The security mode selection controller is configured to determine a number of pending access requests associated with the memory security controller, determine a number of incoming responses from the non-volatile memory to the memory security controller, and select between the first functional safety mode and the second functional safety mode based on at least one of the number of pending access requests or the number of incoming responses.

公开(公告)号：US20250139031A1

公开(公告)日：2025-05-01

申请号：US18498581

申请日：2023-10-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nikhil Sangani ,  Mihir Mody ,  Malav Shah ,  Athavan Arasumani ,  Shailesh Ghotgalkar

IPC: G06F13/20

Abstract: Various examples disclosed herein relate to deterministically controlling interconnect operations to provide dynamic power gating for a system. In an example, a microcontroller unit (MCU) is provided that includes a group of processing devices, a group of target resources, interconnect circuitry, and clock control circuitry. The interconnect circuitry connects the group of processing devices to the group of target resources. The clock control circuitry is coupled to the interconnect circuitry. The clock control circuitry is configured to identify an upcoming occurrence of a communication between a pair of devices comprised of one of the processing devices and one of the target resources, and prior to the occurrence of the communication, enable a clock associated with a path through the interconnect circuitry between the pair of devices.

公开(公告)号：US12111778B2

公开(公告)日：2024-10-08

申请号：US17558252

申请日：2021-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Mody ,  Niraj Nandan ,  Hetul Sanghvi ,  Brian Chae ,  Rajasekhar Reddy Allu ,  Jason A. T. Jones ,  Anthony Lell ,  Anish Reghunath

IPC: G06F13/16 ,  G06F13/28 ,  G06T1/20 ,  H04N5/765

CPC classification number: G06F13/1668 ,  G06F13/28 ,  G06T1/20 ,  H04N5/765

Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.

公开(公告)号：US20240201997A1

公开(公告)日：2024-06-20

申请号：US18068030

申请日：2022-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Mody ,  Kedar Chitnis ,  Prithvi Shankar Yeyyadi Anantha ,  Shailesh Ghotgalkar ,  Donald Steiss ,  Mohammad Asif Farooqui ,  Nikhil Sangani ,  Sriraj Chellappan

IPC: G06F9/345 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50

CPC classification number: G06F9/345 ,  G06F9/30021 ,  G06F9/3877 ,  G06F9/5016 ,  G06F9/5027

Abstract: Various embodiments disclosed herein relate to compute offloading by supplying operands to hardware accelerators from central processing units. An example embodiment includes a system configured to perform compute offloading. The system comprises a processing unit configured to write data to a memory and a memory adaptor bridge coupled between the processing unit and the memory. The memory adaptor bridge is configured to, in response to an attempt by the processing unit to write an operand to a memory location mapped to a function of a hardware accelerator, write the operand to a different memory location accessible by the hardware accelerator. The memory adaptor bridge is further configured to obtain a result of the function performed on the operand by the hardware accelerator and provide the result of the function to a memory location accessible by the processing unit.

公开(公告)号：US11863713B2

公开(公告)日：2024-01-02

申请号：US16669138

申请日：2019-10-30

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Brian Chae ,  Mihir Mody ,  Rajasekhar Reddy Allu

IPC: H04N17/00 ,  H04N5/14 ,  H04N7/18

CPC classification number: H04N17/004 ,  H04N5/144 ,  H04N7/183

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for image frame freeze detection. An example hardware accelerator includes a core logic circuit to generate second image data based on first image data associated with a first image frame, the second image data corresponding to at least one of processed image data, transformed image data, or one or more image data statistics, a load/store engine (LSE) coupled to the core logic circuit, the LSE to determine a first CRC value based on the second image data obtained from the core logic circuit, and a first interface coupled to a second interface, the second interface coupled to memory, the first interface to transmit the first CRC value obtained from the memory to a host device.

公开(公告)号：US20230385114A1

公开(公告)日：2023-11-30

申请号：US18175333

申请日：2023-02-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Mody ,  Niraj Nandan ,  Rajasekhar Allu ,  Ankur Ankur

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/54

CPC classification number: G06F9/5027 ,  G06F9/4881 ,  G06F9/544

Abstract: A data processing device includes a plurality of hardware accelerators, a scheduler circuit, and a blocking circuit. The scheduler circuit is coupled to the plurality of hardware accelerators, and includes a plurality of hardware task schedulers. Each hardware task scheduler is coupled to a corresponding hardware accelerator, and is configured to control execution of the task by the hardware accelerator. The blocking circuit is coupled to the plurality of hardware accelerators and configured to inhibit communication between a first hardware accelerator and a second hardware accelerator of the plurality of hardware task schedulers.

公开(公告)号：US11789836B2

公开(公告)日：2023-10-17

申请号：US17462046

申请日：2021-08-31

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Hetul Sanghvi ,  Mihir Mody ,  Gary Cooper ,  Anthony Lell

IPC: G06F11/00 ,  G06F11/273 ,  G06F11/22 ,  G06F9/48 ,  G06F13/28 ,  G06F13/16

CPC classification number: G06F11/2733 ,  G06F9/4843 ,  G06F11/2242 ,  G06F13/1668 ,  G06F13/28

Abstract: A system to implement debugging for a multi-threaded processor is provided. The system includes a hardware thread scheduler configured to schedule processing of data, and a plurality of schedulers, each configured to schedule a given pipeline for processing instructions. The system further includes a debug control configured to control at least one of the plurality of schedulers to halt, step, or resume the given pipeline of the at least one of the plurality of schedulers for the data to enable debugging thereof. The system further includes a plurality of hardware accelerators configured to implement a series of tasks in accordance with a schedule provided by a respective scheduler in accordance with a command from the debug control. Each of the plurality of hardware accelerators is coupled to at least one of the plurality of schedulers to execute the instructions for the given pipeline and to a shared memory.

公开(公告)号：US20230229610A1

公开(公告)日：2023-07-20

申请号：US18190242

申请日：2023-03-27

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Rajasekhar Reddy Allu ,  Brian Chae ,  Mihir Mody

IPC: G06F13/28 ,  G06F9/48 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F13/28 ,  G06F9/4881 ,  G06F13/1673 ,  G06F13/4027 ,  G06F2213/0038

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed herein to enable data aggregation and pattern adaptation in hardware acceleration subsystems. In some examples, a hardware acceleration subsystem includes a first scheduler, a first hardware accelerator coupled to the first scheduler to process at least a first data element and a second data element, and a first load store engine coupled to the first hardware accelerator, the first load store engine configured to communicate with the first scheduler at a superblock level by sending a done signal to the first scheduler in response to determining that a block count is equal to a first BPR value and aggregate the first data element and the second data element based on the first BPR value to generate a first aggregated data element.