公开(公告)号：US20230045722A1

公开(公告)日：2023-02-09

申请号：US17468637

申请日：2021-09-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Zhiguo Li ,  Chi Ren ,  Xiaojuan Gao ,  Boon Keat Toh

IPC: H01L27/11531 ,  H01L27/11573 ,  H01L29/423 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L21/28 ,  H01L29/66

Abstract: A semiconductor memory device includes a semiconductor substrate, a select gate on the semiconductor substrate, a control gate disposed adjacent to the select gate and having a first sidewall and a second sidewall, and a charge storage layer between the control gate and the semiconductor substrate. The control gate includes a third sidewall close to the second sidewall of the select gate, a fourth sidewall opposite to the third sidewall, and a non-planar top surface between the third sidewall and the fourth sidewall. The non-planar top surface includes a first surface region that descends from the third sidewall to the fourth sidewall. The charge storage layer extends to the second sidewall of the select gate.

公开(公告)号：US10825522B2

公开(公告)日：2020-11-03

申请号：US16173406

申请日：2018-10-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Zhaobing Li ,  Chi Ren

IPC: G11C16/04 ,  H01L45/00 ,  G11C13/00 ,  H01L27/11517

Abstract: A structure of nonvolatile memory device includes a substrate, having a logic device region and a memory cell region. A first gate structure for a low-voltage transistor is disposed over the substrate in the logic device region, wherein the first gate structure comprises a single-layer polysilicon. A second gate structure for a memory cell is disposed over the substrate in the memory cell region. The second gate structure includes a gate insulating layer on the substrate. A floating gate layer is disposed on the gate insulating layer, wherein the floating gate layer comprises a first polysilicon layer and a second polysilicon layer as a stacked structure. A memory dielectric layer is disposed on the floating gate layer. A control gate layer is disposed on the memory dielectric layer, wherein the control gate layer and the single-layer polysilicon are originated from a preliminary polysilicon layer in same.

公开(公告)号：US10784185B2

公开(公告)日：2020-09-22

申请号：US16701201

申请日：2019-12-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhao-Bing Li ,  Ju-Bao Zhang ,  Chi Ren

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L25/065 ,  H01L21/66 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor device includes at least one wafer and at least one TSV (through silicon via) structure. The at least one wafer each includes a substrate, an isolation structure, and a conductive pad. The isolation structure is formed in the substrate and extends from a first side of the substrate toward a second side opposite to the first side of the substrate. The conductive pad is formed at a dielectric layer disposed on the first side of the substrate, wherein the conductive pad is electrically connected to an active area in the substrate. The at least one TSV structure penetrates the at least one wafer. The conductive pad contacts a sidewall of the at least one TSV structure, and electrically connects the at least one TSV structure and the active area in the substrate. The isolation structure separates from and surrounds the at least one TSV structure.

公开(公告)号：US10546801B2

公开(公告)日：2020-01-28

申请号：US15678541

申请日：2017-08-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhao-Bing Li ,  Ju-Bao Zhang ,  Chi Ren

IPC: H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L25/065 ,  H01L21/66 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor device includes at least one wafer and at least one TSV (through silicon via) structure. The at least one wafer each includes a substrate, an isolation structure, and a conductive pad. The isolation structure is formed in the substrate and extends from a first side of the substrate toward a second side opposite to the first side of the substrate. The conductive pad is formed at a dielectric layer disposed on the first side of the substrate, wherein the conductive pad is electrically connected to an active area in the substrate. The at least one TSV structure penetrates the at least one wafer. The conductive pad contacts a sidewall of the at least one TSV structure, and electrically connects the at least one TSV structure and the active area in the substrate. The isolation structure separates from and surrounds the at least one TSV structure.

公开(公告)号：US09431256B2

公开(公告)日：2016-08-30

申请号：US13939186

申请日：2013-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Yuan Hsu ,  Zhen Chen ,  Chi Ren ,  Ching-Long Tsai ,  Wei Cheng ,  Ping Liu

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H01L27/115

CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method for manufacturing a semiconductor device includes the following steps. At first, two gate stack layers are formed on a semiconductor substrate, wherein each of the gate stack layers includes a top surface and two side surfaces. A conductive material layer is deposited to conformally cover the top surface and the two side surfaces of each of the gate stack layers. Then, a cap layer is deposited to conformally cover the conductive material layer. Finally, the cap layer and the conductive material layer above the top surface of each of the gate stack layers are removed to leave the cap layer adjacent to the two side surfaces of each of the gate stack layers and covering a portion of the conductive material layer.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 首先，在半导体衬底上形成两个栅极堆叠层，其中每个栅极堆叠层包括顶表面和两个侧表面。 沉积导电材料层以共形地覆盖每个栅极堆叠层的顶表面和两个侧表面。 然后，沉积覆盖层以覆盖导电材料层。 最后，去除盖层和每个栅极堆叠层的顶表面上方的导电材料层，以使覆盖层与每个栅极叠层层的两个侧表面相邻并且覆盖导电材料层的一部分 。

公开(公告)号：US09117847B2

公开(公告)日：2015-08-25

申请号：US14516592

申请日：2014-10-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Yuan Hsu ,  Chi Ren ,  Tzeng-Fei Wen

IPC: H01L21/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/788 ,  H01L21/28 ,  H01L27/115 ,  H01L21/266

CPC classification number: H01L29/66825 ,  H01L21/266 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7881 ,  H01L29/7882

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes the steps of: sequentially forming agate dielectric layer and a first gate layer on a semiconductor substrate, wherein the gate dielectric layer is between the first gate layer and the semiconductor substrate; forming at least an opening in the first gate layer; forming a first dielectric layer conformally on the semiconductor substrate wherein the first dielectric layer covers the first gate layer; and forming a second gate layer filling the opening and overlapping the first gate layer.

Abstract translation: 公开了制造半导体器件的方法。 该方法包括以下步骤：在半导体衬底上依次形成玛瑙电介质层和第一栅极层，其中栅介电层位于第一栅层和半导体衬底之间; 在所述第一栅极层中形成至少一个开口; 在所述半导体衬底上共形形成第一电介质层，其中所述第一电介质层覆盖所述第一栅极层; 以及形成填充所述开口并与所述第一栅极层重叠的第二栅极层。

公开(公告)号：US08921913B1

公开(公告)日：2014-12-30

申请号：US13923374

申请日：2013-06-21

Applicant: United Microelectronics Corp.

Inventor： Cheng-Yuan Hsu ,  Zhaobing Li ,  Chi Ren ,  Ching-Long Tsai ,  Wei Cheng

IPC: H01L21/336 ,  H01L21/28

CPC classification number: H01L21/28273 ,  H01L21/3212

Abstract: A floating gate forming process includes the following steps. A substrate containing active areas isolated from each other by isolation structures protruding from the substrate is provided. A first conductive material is formed to conformally cover the active areas and the isolation structure. An etch back process is performed on the first conductive material to respectively form floating gates separated from each other in the active areas.

Abstract translation: 浮栅形成工艺包括以下步骤。 提供了包含通过从衬底突出的隔离结构彼此隔离的有源区的衬底。 第一导电材料形成为保形地覆盖有源区域和隔离结构。 对第一导电材料进行回蚀处理，以分别形成在有源区域中彼此分离的浮动栅极。